Hardware Design Engineer 3 - Contract - Bangalore

Sunrise Biztech Systems; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Sunrise Biztech Systems in Bengaluru is seeking a Hardware Design Engineer 3 with extensive ASIC experience. The role focuses on advanced verification, low‑power methods, and signoff across RTL to full-chip stages.

The candidate will work with cross‑functional teams, utilize UPF/CPF for low‑power validation, and employ tools like VC-LP and Formality/LEC to ensure high-quality silicon and successful signoff within a 12‑month contract.

Qualifications

• 8+ years of experience in hardware design and verification for ASICs.
• Expertise in FCCheck/VSI closure for digital ASICs.
• Low-Power Validation using UPF/CPF across RTL, Synthesis, PnR and Full-Chip.
• Hands-on experience with VC-LP (Synopsys/Cadence).
• Formality/LEC across RTL Gate PnR and full design cycle.
• Debug and close Low-Power and Equivalence mismatches for signoff.

Responsibilities

• Collaborate with cross-functional teams to ensure design quality and signoff closure.
• Diagnose and fix low-power and equivalence issues at RTL, gate level and full chip stages.
• Support signoff activities across PnR and post-layout verification.
• Provide input for design improvements to reduce power and ensure timing/area goals.

Skills

FCCheck/VSI closure

Low-Power Validation

RTL/Synthesis/PnR experience

Formality/LEC

Signoff closure

Low-Power/Equivalence debugging

Education

B.E./B.Tech/M.E./M.Tech

Tools

VC-LP (Synopsys/Cadence)

Conformal ECO

Formality/LEC tooling

Job description

Position: Hardware Design Engineer 3

Experience: 8+ Years

Location: Bangalore

Contract Tenure: 12 months

Education: B.E./B.Tech/M.E./M.Tech

Key Skills & Responsibilities:

• 3+ years of experience in FCCheck/VSI closure for digital ASIC chips.
• Strong expertise in Low-Power Validation using UPF/CPF across RTL, Synthesis, PnR and Full-Chip levels.
• Hands-on experience with VC-LP (Synopsys/Cadence).
• Expertise in Formality/LEC across RTL Gate PnR and full design cycle.
• Debug and close Low-Power and Equivalence mismatches for signoff.
• Experience with Conformal ECO is an added advantage.
• Collaborate with cross-functional teams for design quality and signoff closure.