FPGA RTL Design Engineer

Epergne Solutions; Chennai District; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Epergne Solutions is seeking an experienced FPGA RTL Design Engineer to join our team in Chennai, Tamil Nadu. The ideal candidate will have strong expertise in VHDL and work on advanced 5G and wireless communication products. Key responsibilities include designing FPGA architecture, developing high-performance solutions, and collaborating with firmware teams. The position also involves validation and optimization of designs for power, performance, and area. We value strong debugging skills and experience in high-speed packet processing.

Qualifications

• Strong experience in FPGA RTL design using VHDL.
• Experience in high-speed packet processing required.
• Good understanding of synthesis, STA, and timing closure.

Responsibilities

• Understand packet processing requirements from system architects.
• Design FPGA RTL architecture and microarchitecture.
• Develop and implement RTL using VHDL.

Skills

FPGA RTL design using VHDL

High-speed packet processing

Debugging and problem-solving

Understanding of FPGA design flow

Knowledge of DSP fundamentals

Tools

Altera Agilex

AMD Zynq RFSoC

UVM/System Verilog

Job description

We are looking for an experienced FPGA RTL Design Engineer with strong expertise in VHDL and high-speed packet processing. The candidate will work on advanced 5G/wireless communication products and develop high-performance FPGA-based solutions.

Key Responsibilities:

• Understand packet processing requirements from system architects
• Design FPGA RTL architecture and microarchitecture
• Develop and implement RTL using VHDL
• Perform functional verification, linting, synthesis, and timing closure
• Validate FPGA designs and optimize performance
• Work with verification and firmware teams for integration
• Support board bring-up and debugging activities
• Optimize designs for power, performance, and area (PPA)

Required Skills:

• Strong experience in FPGA RTL design using VHDL
• Experience in high-speed packet processing
• Good understanding of FPGA design flow
• Knowledge of synthesis, STA, and timing closure
• Strong debugging and problem-solving skills
• Experience in wireless communication or 5G domain is preferred
• Exposure to Altera Agilex or AMD Zynq RFSoC is an advantage
• Knowledge of DSP fundamentals and protocols like 5G, LTE, Wi-Fi is a plus
• Familiarity with UVM/System Verilog is preferred