FPGA RTL Design Engineer / Senior Engineer

FiniteHR Consulting; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

FiniteHR Consulting is seeking an experienced FPGA RTL Design Engineer/Senior Engineer for our client SeviTech in Bengaluru, India.

The role entails IP/micro-architecture development, RTL coding, and verification, requiring a B. Tech or M. Tech with 8-10 years in related field and strong skills in Verilog and logic design. Immediate joiners preferred.

Qualifications

• B. Tech. or M. Tech. with 8 to 10 years of experience.
• Experience in Logic design/micro-architecture/RTL coding is a must.
• Must have expertise in Verilog.

Responsibilities

• Responsible for IP/sub-system level micro-architecture development and RTL coding.
• Prepare block/sub-system level timing constraints.
• Perform basic verification in IP Verification environment or FPGA.

Skills

Logic design

Micro-architecture

RTL coding

Verilog

AMBA protocols (AXI, AHB, APB)

Synthesis

Timing concepts in Xilinx FPGA

DDR / USB / PCIe controller design

Multi Clock designs

Asynchronous interface

Education

B. Tech.

M. Tech.

Tools

Lint

CDC

Simulation tools

Job description

• Full-time

Company Description

Finite HR Consulting

Job Description

Our Client SeviTech is looking for FPGA RTL Design Engineer / Senior Engineer

About our Client: http://sevitechsystems.com/

Job Type: Permanent

Job Description:

• You will be responsible for IP / sub-system level micro-architecture development and RTL coding.
• Prepare block/sub-system level timing constraints.
• Perform basic verification either in IP Verification environment or FPGA.

Desired Skills and Experience

• B. Tech. or M. Tech. with 8 to 10 years of experience.
• Experience in Logic design / micro-architecture / RTL coding is a must.
• Expertise in Verilog is a must.
• Should have knowledge of AMBA protocols - AXI, AHB, APB.
• Experience in Synthesis / Understanding of timing concepts in Xilinx FPGA Implementation is required. FPGA Proto-typing experience is a must.
• Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus.
• Hands on experience in Multi Clock designs, Asynchronous interface are a must.
• Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.
• Knowledge of low power concepts and experience is a plus.
• This is an Immediate Opportunity candidate with less than one month notice will be preferred.

Qualifications

M. Tech. / B. Tech.

Additional Information

This is an Immediate Opportunity; candidates with less than one month notice will be preferred.