FPGA Design Lead

Capgemini Engineering; Bengaluru; On-site; INR 1,400,000 - 2,300,000; Full time

Job summary

Capgemini Engineering in Bengaluru seeks experienced FPGA Design Engineers and Technical Leads to work on cutting-edge 5G and PCIe technologies.

You will contribute to architecture, RTL development, verification, and integration of high-performance FPGA-based communication systems. The role also involves mentoring junior engineers for lead positions.

Qualifications

• Experience in FPGA architecture and RTL development.
• Strong background in Verilog, VHDL, and SystemVerilog.
• Familiarity with high-speed interfaces and communication protocols.
• Experience with FPGA synthesis, place & route, STA, and timing closure.
• Ability to lead design reviews and mentor junior engineers.

Responsibilities

• Design and implement FPGA-based solutions for high-performance communication systems.
• Participate in architecture definition, design implementation, verification, and integration activities.
• Develop detailed design specifications and technical documentation.
• Develop and implement block-level RTL using Verilog, VHDL, and SystemVerilog.
• Perform FPGA synthesis, place & route, STA, and timing closure.
• Collaborate with Hardware, Software, Validation, Diagnostics, Signal Integrity, and System Engineering teams.
• Support subsystem bring-up, FPGA debugging, integration, and system validation activities.
• Drive technical discussions, design reviews, and mentor junior engineers (for Lead positions).

Skills

FPGA architecture

RTL development

Verilog

VHDL

SystemVerilog

STA / timing analysis

Job description

Notice Period : Preferred Immedaite joiners.

We are looking for highly skilled FPGA Design Engineers and Technical Leads with strong experience in FPGA architecture, RTL development, high-speed interfaces, and communication protocols. This role offers an opportunity to work on cutting-edge 5G and next-generation PCIe technologies.

Key Responsibilities

• Design and implement FPGA-based solutions for high-performance communication systems.
• Participate in architecture definition, design implementation, verification, and integration activities.
• Develop detailed design specifications and technical documentation.
• Develop and implement block-level RTL using Verilog, VHDL, and SystemVerilog.
• Perform FPGA synthesis, place & route, static timing analysis (STA), and timing closure.
• Collaborate with Hardware, Software, Validation, Diagnostics, Signal Integrity, and System Engineering teams.
• Support subsystem bring-up, FPGA debugging, integration, and system validation activities.
• Drive technical discussions, design reviews, and mentor junior engineers (for Lead positions).