FPGA Emulation Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru seeks a senior FPGA engineer to develop FPGA emulation and prototyping platforms for next-generation SoCs, enabling early software bring-up and pre-silicon validation.

You will convert ASIC RTL to FPGA-ready designs, drive timing closure, collaborate with RTL, DV, and embedded software teams, and develop automation to speed builds and deployment.

Qualifications

• 6–10 years of experience in FPGA Emulation, FPGA Prototyping, or SoC Bring-up.
• Strong hands-on with Verilog/SystemVerilog and FPGA implementation.
• Experience with FPGA prototyping platforms and flow automation.

Responsibilities

• Develop and maintain FPGA emulation and prototyping platforms for complex SoCs.
• Convert ASIC RTL into FPGA-ready designs, including partitioning and timing closure.
• Enable pre-silicon software bring-up and system validation.
• Drive FPGA implementation and RTL optimizations for multi-clock designs.
• Debug complex SoC issues using waveform analysis and lab validation.
• Collaborate with RTL, DV, Architecture, Embedded Software and Post-Silicon teams.
• Develop automation to speed FPGA build, debug, and deployment.

Skills

FPGA Emulation

FPGA Prototyping

SoC Bring-up

Verilog/SystemVerilog

Clock/Reset design

High-speed interfaces

Synthesis/Place & Route

Python scripting

Tcl/Perl scripting

Tools

Vivado

Synplify

Quartus

Libero SoC

VCS

Verdi

Questa/Xcelium

HAPS

ProFPGA

ZeBu

Palladium

Veloce

RUMI

Job description

Join our silicon engineering team to develop and deploy FPGA emulation and prototyping platforms for next-generation SoCs. You will enable early software bring-up, accelerate pre-silicon validation, and drive first-pass silicon success.

What You'll Do

• Develop and maintain FPGA emulation and prototyping platforms for complex SoCs.
• Convert ASIC RTL into FPGA-ready designs, including partitioning, synthesis, implementation, and timing closure.
• Enable pre-silicon software bring-up, system validation, and hardware/software co-debug.
• Drive FPGA implementation, multi-clock design closure, and FPGA-specific RTL optimizations.
• Debug complex SoC issues using waveform analysis, hardware instrumentation, and lab validation.
• Collaborate with RTL, Design Verification, Architecture, Embedded Software, and Post-Silicon teams to resolve system-level issues.
• Develop automation to improve FPGA build, debug, and deployment efficiency.

What You Bring

• 6–10 years of experience in FPGA Emulation, FPGA Prototyping, or SoC Bring-up.
• Strong hands-on experience with Verilog/SystemVerilog, FPGA implementation, synthesis, place & route, and timing closure.
• Experience with FPGA prototyping/emulation platforms such as HAPS, ProFPGA, ZeBu, Palladium, Veloce, RUMI, or equivalent.
• Strong understanding of SoC architecture, clock/reset design, memory subsystems, and high-speed interfaces.
• Hands-on experience with one or more protocols: PCIe, DDR4/DDR5, LPDDR4/5, AXI, APB, Ethernet, USB, JESD204B/C, CXL.
• Proficiency with FPGA development tools such as Vivado, Synplify, Quartus, Libero SoC, and simulation/debug tools including VCS, Verdi, Questa/Xcelium.
• Experience with scripting using Python, Tcl, or Perl for flow automation.

Preferred Qualifications

• Experience with ASIC Emulation, hardware/software co-verification, and pre-silicon validation.
• Exposure to embedded firmware bring-up and system-level debug.
• Strong debugging, problem-solving, and cross-functional collaboration skills.