FPGA Design & ASIC Prototyping Engineer

Mettlesemi Systems; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Mettlesemi Systems in Bengaluru is looking for an FPGA Design & ASIC Prototyping Engineer to join our team. This role involves collaborating on complex SoC designs, performing RTL design, and leading emulation efforts.

The ideal candidate possesses substantial experience in FPGA design and related methodologies, including Synopsys HAPS and Cadence Palladium. Candidates should have a passion for technology trends and excellent communication skills to navigate challenges in development.

Qualifications

• 12+ years of relevant experience with a Bachelor's degree or 11+ years with a Master's degree.
• 5 years of experience in emulation/FPGA-based ASIC prototyping and FPGA Design.
• Experience in verification methodologies like UVM/OVM is a plus.

Responsibilities

• Collaborate within a team to verify, emulate, or prototype complex system-on-a-chip designs.
• Conduct synthesis, PNR, and timing analysis of RTL on prototyping and emulation platforms.
• Work closely with design engineers to identify critical verification scenarios.

Skills

FPGA design techniques

RTL Design

Verilog/System Verilog

Perl

Python

Shell scripts

Education

Bachelor's degree in Electrical/Electronics Engineering or Master's degree in Electrical Engineering/Computer Science

Tools

Synopsys HAPS

Cadence Palladium

Siemens Veloce

ZEBU

Job description

About the role:

Join our dynamic team as an FPGA Design & ASIC Prototyping Engineer, where your expertise in FPGA design, RTL design, and Prototyping will drive cutting-edge technology advancements. Collaborate on complex system-on-a-chip designs using platforms like Synopsys HAPS and Zebu. Lead RTL porting, synthesis, and timing analysis, and be at the forefront of innovation in digital systems.

Qualifications, Experience & Desired Skills:

• Bachelor's degree in Electrical/Electronics Engineering with 12+ years of relevant experience or a master's degree in Electrical Engineering or Computer Science with 11+ years of relevant experience.
• Proficient in FPGA design techniques, RTL Design, and associated tools and processes.
• Minimum 5 years of experience in emulation/FPGA based ASIC prototyping, and FPGA Design.
• Extensive experience in Verilog/System Verilog-based verification at the Subsystem and Full chip level, including transactor-based verification. Knowledge of verification methodologies like UVM/OVM is a plus.
• Strong command of RTL languages (e.g., VHDL, Verilog), in-circuit emulation, simulation acceleration, and FPGA prototyping.
• Experienced with emulation/prototyping tools and methodologies, with hands‑on experience in mapping complex SOC designs into multi‑FPGA platforms, including Synopsys HAPS. ZEBU, Cadence Palladium, Siemens Veloce
• Proven expertise in emulation-based verification methodologies, including the development of complex emulation workflow environments and model building for prototyping or emulation.
• Proficiency in STA/timing closure, wrapper creation, HDL simulation, synthesis, and memory modelling for prototyping/emulation.
• Working knowledge of Perl, Python, and Shell scripts.
• Experience with digital systems based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols.
• Familiarity with SOC boot flow, basic test case creation, clocking, and platform bring-up in Emulators or Silicon is desired.
• Passion for staying updated with tech trends and excellent verbal and written communication skills for issue communication and corrective action reporting.

Roles & Responsibilities:

• Collaborate within a team to verify, emulate, or prototype complex system-on-a-chip designs. Work closely with design engineers to identify critical verification scenarios.
• Perform RTL Design and port ASIC RTL for FPGA prototyping and emulation platforms, such as HAPS, Synopsys ZEBU, Cadence Palladium, or Siemens Veloce.
• Conduct synthesis, PNR (Place and Route), and timing analysis of RTL on industry‑standard prototyping and emulation platforms.