FPGA Design Engineer

Acldigital

Bengaluru

On-site

INR 1,200,000 - 2,500,000

Full time

14 days+
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Job summary

Acldigital in Bangalore is seeking an experienced FPGA Design Engineer to own complex FPGA projects end-to-end. You will design and verify FPGA logic, implement high-speed interfaces, and collaborate with RTL, verification and software teams.

The ideal candidate has 8+ years of hands-on FPGA experience, strong knowledge of Verilog/SystemVerilog/VHDL, and hands-on timing closure and debugging skills. This role requires immediate joiners and is based in Bangalore.

Qualifications

  • 8+ years in FPGA design engineering.
  • Strong FPGA experience and verification.
  • Hands-on verification with high-speed interfaces (Ethernet, PCIe, DDR).

Responsibilities

  • Design and implement FPGA logic using Verilog/SystemVerilog/VHDL.
  • Develop high-speed interfaces such as PCIe, Ethernet, DDR, and SerDes.
  • Perform timing closure, synthesis, implementation, and hardware bring-up.
  • Debug FPGA designs on hardware using industry-standard tools.
  • Collaborate with RTL, verification, and software teams.

Skills

FPGA Design
FPGA Verification
High-speed Interfaces
Timing Closure
Debugging
Digital Design Fundamentals
Verilog/SystemVerilog/VHDL
Xilinx/AMD/Intel Tool Flows

Job description

Experience: 8+ Years

Location: Bangalore

Notice Period: Immediate joiners Preferred

Requirements
  • Minimum 8+ years in FPGA Design Engineer
  • Strong experience in FPGA
  • Hands‑on experience in FPGA Verification
  • FPGA verification, high‑speed interfaces (Ethernet, PCIe, DDR, etc.)
Ideal Candidate
  • 8+ years ofFPGA design experience.
  • Strongknowledge of Xilinx/AMD or Intel FPGA tool flows.
  • Experiencewith high-speed interfaces (Ethernet, PCIe, DDR, etc.).
  • Good debuggingand timing closure skills.
  • Strongunderstanding of digital design fundamentals.
What the Role Involves
  • Design andimplement FPGA logic using Verilog/SystemVerilog/VHDL.
  • Develophigh-speed interfaces such as PCIe, Ethernet, DDR, and SerDes.
  • Performtiming closure, synthesis, implementation, and hardware bring-up.
  • Debug FPGAdesigns on hardware using industry-standard tools.
  • Collaboratewith RTL, verification, and software teams.
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