ASIC Emulation Engineer / Technical Leader

123 Cisco Systems (India) Private Limited; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

123 Cisco Systems (India) Private Limited in Bengaluru is looking for an experienced engineer to define and develop emulation environments for networking ASICs. This role requires a strong background in design emulation, fluent in SystemVerilog or Verilog, and insightful knowledge in debugging and verification flows.

In addition to technical expertise, the candidate must demonstrate excellent communication skills to coordinate effectively with various teams. The position is ideal for individuals with a Bachelor's degree and several years in related experience, emphasizing leadership in resolving issues.

Qualifications

• 8+ years of experience with a Bachelor's degree or 6+ years with a Master's degree in a relevant field.
• Hands-on experience with emulation platforms and design emulation background.
• Fluent in SystemVerilog or Verilog for emulation development.

Responsibilities

• Define, design, and develop emulation environments for ASICs.
• Work with emulation vendors to troubleshoot issues.
• Develop tests for complex traffic and performance scenarios.

Skills

C/C++

SystemVerilog

Verilog

Python

Scripting

ASIC verification

Education

Bachelor’s degree + 8 years or Master’s degree + 6 years of related experience

Tools

Veloce

Palladium

Zebu

gdb

waveform debuggers

Job description

What You’ll Do

• Define, design and develop emulation environments needed for complex, large‑scale networking ASICs.
• Develop the emulation environment, build netlists, and use them to accelerate the development cycle and detect potential ASIC issues during the pre‑silicon phase.
• Work with leading emulation vendors to troubleshoot issues.
• Develop state‑of‑the‑art emulation environments to evaluate the performance and functionality of multi‑terabit systems.
• Develop emulation infrastructure using C/C++, TCL, Python, etc.
• Develop and test various emulation flows and contribute to different aspects of ASIC verification for bug‑free silicon.
• Collaborate closely with the design and hardware teams to verify the ASIC in emulation and during ASIC bring‑up.
• Work closely with the design, DV, power, and post‑silicon diagnostic teams.
• Assist with test plan design, test implementation, and debugging during the pre‑silicon emulation process.
• Develop tests to generate complex traffic and performance scenarios to catch potential post‑silicon issues during the pre‑silicon phase.

Minimum Qualifications

• Bachelor’s degree + 8 years or Master’s degree + 6 years of related experience.
• Design emulation background with hands‑on experience with emulation platforms such as Veloce, Palladium, Zebu, and experience with compilation, debug, and performance testing.
• Fluent in SystemVerilog or Verilog to work on the emulation infrastructure development.
• In‑depth knowledge of C/C++ and scripting, and ASIC design and verification flow.
• Expertise in RTL development for emulation prototypes.
• System debug experience using tools such as gdb and waveform debuggers.

Preferred Qualifications

• Strong hands‑on experience with scripting programs (e.g., Python, Perl, or similar).
• Strong communication skills and ability to work as a team.
• Post‑silicon functional validation or debugging experience is a plus.
• Knowledge of protocols such as PCIe, I2C, Ethernet.
• Good interpersonal skills and validated leadership to accurately describe issues/improvements and lead the team for on‑time completion.
• Excellent communication skills, both verbal and written.