Field-Programmable Gate Arrays Engineer

ACL Digital; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

A technology services company in Hyderabad is looking for a Principal Engineer specializing in FPGA video solutions. The ideal candidate will have expertise in RTL coding with Verilog, System Verilog, or VHDL, along with a strong understanding of FPGA flow and digital design. Proficiency in Tcl and Python scripting is also required. This full-time position offers a chance to lead impactful engineering projects in a collaborative environment.

Qualifications

• Strong understanding of FPGA flow, logic design, and digital design.
• Experience in FPGA prototyping and emulation.

Responsibilities

• Lead the prototyping and emulation of FPGA solutions.
• Work on RTL coding in Verilog, System Verilog, or VHDL.

Skills

RTL Coding

Verilog

System Verilog

VHDL

Xilinx FPGA architecture

Tcl scripting

Python scripting

Job description

Direct message the job poster from ACL Digital

Expertise RTL Coding in Verilog, System Verilog or VHDL · Strong understanding of FPGA flow, Logic design, Digital design etc. · Knowledge in Xilinx FPGA architecture · Good Knowledge in Tcl, Python scripting.

Interested,please share your updated resume to [e-mail]

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering, Product Management, and Project Management

Industries

Engineering Services and Semiconductor Manufacturing

Location: Hyderabad, Telangana, India

Principal Engineer - FPGA Video Solutions

Lead FPGA prototyping and emulation Engineer