Emulation Architect

Sevya Multimedia; Hyderabad; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

Sevya Multimedia is seeking an experienced verification architect to drive pre-silicon validation using Cadence Palladium Z2/ZX for a multi-core SoC with ARM Cortex and/or RISC-V cores.

You will design emulation environments, develop PCIe models, and ensure robust debug and regression workflows.

Qualifications

• 8+ years in ASIC/SoC verification.
• 4+ years Palladium emulation experience.
• Strong knowledge of ARM/RISC‑V SoC architecture.
• Proficiency in PCIe Gen4/5, TLP/DLLP and power states.

Responsibilities

• Architect end-to-end emulation environment on Cadence Palladium Z2/ZX for a multi-core SoC (ARM Cortex / RISC‑V).
• Define emulation bring-up strategy across multi-million gate designs.
• Design and integrate PCIe-like interface models for emulation.
• Build and maintain ICE connectors and co-emulation bridges to real PCIe host systems.
• Develop emulation-specific IP to overcome clock frequency limitations.
• Define and enforce debug strategies: waveform probing, logging, assertion coverage.
• Collaborate with RTL/firmware/verification leads to map subsystems onto the emulation platform.
• Establish software co-development flows: boot bare-metal and OS images on emulated cores.
• Manage emulation farm scheduling and regression infrastructure.
• Drive emulation-to-silicon correlation analysis and document discrepancies.
• Own design partitioning for hybrid emulation/simulation (Palladium + VCS/Xcelium).
• Champion reuse of verification IP (VIP) across environments.

Skills

Palladium emulation

ARM Cortex / RISC-V

PCIe protocol

SystemVerilog & UVM

Python/Tcl scripting

Xcelium/VCS

Emulation architecture

Tools

Cadence Palladium Z2/ZX

Xcelium

VCS

PCIe TLM/BFM models

Job description

Role Overview

Drive pre-silicon validation strategy and emulation infrastructure for a complex SoC featuring ARM and/or RISC-V cores with high-speed PCIe-class interfaces, using Cadence Palladium Z2/ZX platforms.

Key Responsibilities

• Architect and own the end-to-end emulation environment on Cadence Palladium Z2/ZX for a multi-core SoC (ARM Cortex / RISC-V)
• Define emulation bring-up strategy including partitioning, compile flows, and debug methodology across multi-million gate designs
• Design and integrate PCIe-like interface models (TLM/BFM/synthesizable) for emulation — covering link training, transaction layer, and data path stimulus
• Build and maintain ICE (In-Circuit Emulation) connectors and co-emulation bridges to real PCIe host systems, FPGAs, or target boards
• Develop emulation-specific IP including speed adapters, FIFO bridges, and clock domain crossing helpers to overcome emulation clock frequency limitations
• Define and enforce compile-time and runtime debug strategies: waveform probing, transaction logging, assertion coverage on Palladium
• Collaborate with RTL designers, firmware engineers, and verification leads to map SoC subsystems (CPU, interconnect, PHY, memory controllers) onto the emulation platform
• Establish software co-development flows: boot bare-metal and OS images (Linux/RTOS) on emulated ARM/RISC-V cores, enabling early firmware and driver validation
• Manage emulation farm scheduling, utilization, and regression infrastructure — integrating with LSF/grid job management
• Drive emulation-to-silicon correlation analysis and document discrepancies
• Own design partitioning for hybrid emulation/simulation (Palladium + VCS/Xcelium mixed-signal co-sim)
• Champion reuse of verification IP (VIP) — particularly PCIe, AXI, CHI — across simulation and emulation environments

Required Skills & Experience

• 8+ years in ASIC/SoC verification with 4+ years hands-on Palladium (Z1/Z2/ZX) emulation architecture
• Deep knowledge of ARM (Cortex-A/M/R, AMBA AXI/AHB/CHI) or RISC‑V (RV64GC, RISC‑V International specs) SoC architecture
• Strong understanding of PCIe protocol (Gen 4/5): TLP/DLLP structure, enumeration, power states (L0s/L1/L2), error handling
• Proficiency in SystemVerilog, UVM, and synthesizable testbench design for emulation targets
• Experience with xcelium/VCS and Palladium iDFT/iSX compilation flows
• Scripting fluency: Python, Tcl, Perl, Make/CMake for build and regression automation
• Hands‑on with embedded software bring‑up: U‑Boot, Linux kernel, PCIe drivers on emulated targets

Nice to Have

• Familiarity with IOMMU, GIC/PLIC, DMA subsystem validation
• Background in formal property verification to complement emulation coverage
• Knowledge of power‑aware emulation (UPF/CPF, voltage‑domain isolation testing)