SOC Emulation Engineer

UST; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

UST is seeking an experienced SOC Emulation Engineer to support pre-silicon verification, emulation, and system validation using Zebu and Cadence Palladium. The role requires hands-on bring-up, debugging, performance optimization, and close collaboration with Design, Verification, Firmware, and Silicon Validation teams.

The ideal candidate will have 4+ years in SoC verification/emulation, strong Linux scripting skills (Python, Perl, TCL, Shell), and familiarity with VCS/Xcelium.

Qualifications

• 4+ years of experience in SoC Verification, Emulation, or Validation.
• Hands-on emulation bring-up and debugging experience.
• Strong understanding of digital design and computer architecture.
• Experience with Linux/Unix environments.
• Scripting proficiency in Python, Perl, TCL, or Shell scripting.

Responsibilities

• Develop, build, and maintain SoC emulation environments using Zebu and Cadence Palladium platforms.
• Perform design bring-up, compilation, partitioning, and mapping of RTL designs onto emulation systems.
• Execute validation and verification test suites on emulation platforms.
• Debug RTL, testbench, and hardware‑software integration issues.
• Analyze emulation performance and optimize runtime, memory usage, and visibility.
• Collaborate with Design, Verification, Firmware, and Silicon Validation teams.
• Support pre‑silicon software development and system‑level validation.
• Develop automation scripts to improve emulation workflows and regression execution.
• Generate technical documentation and provide status updates to stakeholders.

Skills

SoC Verification

Emulation

Debugging

Root Cause Analysis

Linux/Unix

Scripting

Firmware bring-up

Tools

Zebu

Cadence Palladium

VCS

Xcelium

Job description

We are seeking an experienced SOC Emulation Engineer with strong expertise in Zebu and Palladium (Palladium Emulation Platform) to support SoC pre-silicon verification, emulation, and system validation activities. The ideal candidate will have hands‑on experience in emulation bring‑up, debugging, performance optimization, and collaboration with design and verification teams.

Key Responsibilities

• Develop, build, and maintain SoC emulation environments using Zebu and Cadence Palladium platforms.
• Perform design bring‑up, compilation, partitioning, and mapping of RTL designs onto emulation systems.
• Execute validation and verification test suites on emulation platforms.
• Debug RTL, testbench, and hardware‑software integration issues.
• Analyze emulation performance and optimize runtime, memory utilization, and debug visibility.
• Collaborate with Design, Verification, Firmware, and Silicon Validation teams.
• Support pre‑silicon software development and system‑level validation.
• Develop automation scripts to improve emulation workflows and regression execution.
• Generate technical documentation and provide status updates to stakeholders.

Required Skills:

• 4+ years of experience in SoC Verification, Emulation, or Validation.
• Strong hands‑on experience with:
• Solid understanding of:
• Digital Design and Computer Architecture
• SoC Integration and Verification Methodologies
• Debugging and Root Cause Analysis
• Experience with Linux/Unix environments.
• Scripting proficiency in Python, Perl, TCL, or Shell scripting.
• Familiarity with simulation tools such as VCS, Xcelium, or equivalent.
• Understanding of firmware/software bring‑up on emulation platforms.