DFT LEAD Engineer

Mirafra Technologies; Bengaluru; Sur place; INR 3 500 000 - 7 000 000; Plein temps

Résumé du poste

Mirafra Technologies in Bengaluru, India is seeking a DFT Lead Engineer to spearhead advanced DFT strategies for complex SoCs. You will oversee architecture, lead implementation, and mentor a team of engineers to deliver robust scan, MBIST, LBIST, boundary scan, and compression solutions.

The role requires 5+ years of hands-on DFT experience, strong ATPG and fault coverage skills, and proficiency with Synopsys Tessent and Cadence tools.

Qualifications

• Bachelor's or Master's in Electronics/Electrical Eng.
• 5+ years of hands-on DFT experience.
• Experience with Scan Insertion, ATPG, MBIST, JTAG, and Compression methodologies.
• Experience with EDA tools (Synopsys/Tessent/Cadence).

Responsabilités

• Lead DFT strategy, architecture, and implementation for complex SoCs.
• Develop and integrate Scan, MBIST, LBIST, Boundary Scan, and Compression techniques.
• Collaborate with Design, Verification, Physical Design, and Product Engineering teams.
• Drive ATPG generation, fault coverage analysis, and silicon bring-up activities.
• Mentor junior DFT engineers and lead technical reviews.

Connaissances

DFT experience

Debugging

Problem solving

Formation

Bachelor's/Master's degree in Electronics or Electrical Engineering

Outils

Synopsys

Tessent

Cadence

Description du poste

Mirafra Technologies is HIRING for #DFT LEAD Engineers!!

Key Responsibilities

• Lead DFT strategy, architecture, and implementation for complex SoCs
• Develop and integrate Scan, MBIST, LBIST, Boundary Scan, and Compression techniques
• Collaborate with Design, Verification, Physical Design, and Product Engineering teams
• Drive ATPG generation, fault coverage analysis, and silicon bring-up activities
• Mentor junior DFT engineers and lead technical reviews

Required Qualifications

• Bachelor's/Master's degree in Electronics, Electrical Engineering, or related field
• 5+ years of hands‑on DFT experience
• Strong expertise in Scan Insertion, ATPG, MBIST, JTAG, and Compression methodologies
• Experience with industry‑standard EDA tools (Synopsys/Tessent/Cadence)
• Strong debugging and problem‑solving skills

Experience: 5-15 Yrs.

Notice Period :- 0- 30 Days (Early Joiner's are preferred).