DFT Engineer

Cyient; Hyderabad; Presencial; INR 1 200 000 - 2 400 000; Tempo integral

Resumo da oferta

Cyient seeks a skilled DFT Engineer to support Qualcomm SoC development programs. The candidate will drive DFT architecture, scan insertion, ATPG generation, MBIST/LBIST integration, pattern validation, and silicon bring-up for complex mobile, automotive, and high‑performance SoCs.

You will collaborate with design, physical design, and verification teams to secure DFT signoff, support first silicon bring-up, and debug manufacturing test issues with ATE teams to improve yield.

Qualificações

• Strong knowledge of Scan Architecture, Scan Compression, ATPG, MBIST/LBIST, JTAG/Boundary Scan, and related fault modeling.
• Experience with DFT signoff methodologies.
• Experience in RTL and gate-level DFT verification.

Responsabilidades

• Perform RTL and gate-level DFT verification.
• Validate scan functionality and test modes through simulation.
• Work with design, physical design, and verification teams for DFT signoff.
• Support first silicon bring-up and failure analysis.
• Collaborate with ATE teams for production test development.
• Debug manufacturing test issues and improve yield.

Conhecimentos

DFT Architecture

Scan Insertion

ATPG

MBIST/LBIST

JTAG/Boundary Scan

Fault Modeling

DFT Signoff Methodologies

Unix/Linux Shell Scripting

Formação académica

Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or related field

Ferramentas

Cadence Modus

Descrição da oferta de emprego

We are seeking a highly skilled DFT Engineer to support Qualcomm SoC development programs. The candidate will be responsible for DFT architecture implementation, scan insertion, ATPG generation, MBIST/LBIST integration, pattern validation, and silicon bring-up activities for complex mobile, automotive, and high-performance SoC designs.

Key Responsibilities

DFT Implementation

• Develop and implement DFT architectures for advanced SoC designs.
• Perform scan insertion and scan chain validation using industry-standard EDA tools.
• Integrate and verify DFT features including:
  • Scan Compression
  • EDT
  • MBIST
  • LBIST
  • Boundary Scan (JTAG/IEEE 1149.1)
  • OCC (On-Chip Clock Controller)

ATPG & Pattern Generation

• Generate ATPG patterns for stuck-at, transition, path-delay, and bridge fault coverage.
• Analyze fault coverage and optimize pattern count.
• Debug DRC violations and pattern simulation failures.

Verification & Validation

• Perform RTL and gate-level DFT verification.
• Validate scan functionality and test modes through simulation.
• Work closely with design, physical design, and verification teams for DFT signoff.
• Support first silicon bring-up and failure analysis.
• Collaborate with ATE teams for production test development.
• Debug manufacturing test issues and improve yield.

Cross-Functional Collaboration

• Interface with Architecture, RTL Design, Physical Design, STA, and Product Engineering teams.

Required Skills

Technical Skills

• Strong understanding of:
  • Scan Architecture
  • Scan Compression
  • ATPG
  • MBIST/LBIST
  • JTAG/Boundary Scan
  • Fault Modeling
  • DFT Signoff Methodologies

EDA Tools

• Experience with one or more:
  • Cadence Modus

Languages & Scripting

• Unix/Linux Shell Scripting

Debug Skills

• Scan chain debugging
• ATPG pattern analysis
• Silicon failure diagnosis

Preferred Qualifications

• Experience on Qualcomm Snapdragon, Automotive, AI/ML, DSP, or Modem SoCs.
• Exposure to low-power DFT methodologies.
• Knowledge of UPF/CPF and power-aware testing.
• Understanding of advanced-node designs (7nm, 5nm, 4nm, 3nm).
• Prior silicon bring-up and yield improvement experience.

Education

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related field.

Keywords

DFT, Scan Insertion, ATPG, MBIST, LBIST, JTAG, Boundary Scan, Tessent, Modus, DFT Compiler, TestMAX, Silicon Bring-up, OCC, Compression, Fault Coverage, SoC, Qualcomm, Snapdragon.