DFT Design Engineer

Intel; Bengaluru; Hybrid; INR 2,800,000 - 4,200,000; Full time

Job summary

Intel India in Bengaluru seeks a senior DFT engineer to design, implement, validate, and debug DFT solutions ensuring manufacturability, test coverage, and silicon quality across IP and SoC programs.

You'll drive TAP/JTAG and IJTAG infrastructures, Boundary Scan, MBIST, and ATPG patterns, collaborate with Design, Verification, and Manufacturing teams, and lead technical reviews to improve DFT methodologies and sign-off across the product lifecycle.

Qualifications

• Bachelor’s degree in Electrical/ Electronics/ Computer Engineering or related field with 10+ years of experience.
• Master’s degree in Electrical Engineering, Microelectronics, or VLSI with 8+ years of experience.
• Experience with Scan Insertion, DFT features, RTL design for DFT and verification.

Responsibilities

• Design, implement, validate, and debug DFT solutions for manufacturability and silicon quality.
• Develop and validate TAP/JTAG, IJTAG infrastructures, Boundary Scan, MBIST, and ATPG patterns.
• Collaborate with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams.
• Validate RTL and Gate-Level Simulation, perform root-cause analysis of DFT failures, drive process improvements.

Skills

TAP/JTAG

IJTAG (IEEE 1687)

Boundary Scan (IEEE 1149.1)

MBIST

Scan Compression

ATPG

Verilog/SystemVerilog

Tcl/Perl/Python scripting

DFT verification

silicon debug

communication skills

technical leadership

Education

Bachelor's Degree in Electrical Engineering / Electronics Engineering / Computer Engineering / Computer Science

Master's Degree in Electrical Engineering / Microelectronics / VLSI

Job description

• Design, implement, validate, and debug Design-for-Test (DFT) solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs.
• Responsibilities include development and validation of TAP/JTAG and IJTAG infrastructures, Boundary Scan (BSCAN), MBIST, Scan/ATPG methodologies, and associated test collateral such as ICL, PDL, BSDL, and ATPG patterns. The role requires driving test access, pattern generation, coverage optimization, memory test validation, and debug of scan, at-speed, and silicon bring-up issues while ensuring robust DFT integration across the product lifecycle.
• The engineer collaborates closely with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness and signoff.
• Key responsibilities include RTL and Gate-Level Simulation (GLS) validation, root-cause analysis and resolution of DFT-related failures, adoption of DFT methodologies and best practices, and leadership of technical reviews and continuous process improvements.
• Required expertise includes TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, Scan Compression, ATPG, Verilog/System Verilog, Tcl/Perl/Python scripting, DFT verification, silicon debug, and strong communication and technical leadership skills.

Job Details

• Design, implement, validate, and debug Design-for-Test (DFT) solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs.
• Responsibilities include development and validation of TAP/JTAG and IJTAG infrastructures, Boundary Scan (BSCAN), MBIST, Scan/ATPG methodologies, and associated test collateral such as ICL, PDL, BSDL, and ATPG patterns. The role requires driving test access, pattern generation, coverage optimization, memory test validation, and debug of scan, at-speed, and silicon bring-up issues while ensuring robust DFT integration across the product lifecycle.
• The engineer collaborates closely with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness and signoff.
• Key responsibilities include RTL and Gate-Level Simulation (GLS) validation, root-cause analysis and resolution of DFT-related failures, adoption of DFT methodologies and best practices, and leadership of technical reviews and continuous process improvements.
• Required expertise includes TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, Scan Compression, ATPG, Verilog/System Verilog, Tcl/Perl/Python scripting, DFT verification, silicon debug, and strong communication and technical leadership skills.

Qualifications

• Candidate must have a Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience Or
• Master's Degree in Electrical Engineering, Microelectronics, VLSI or related field with 8+ years of experience.
• Scan Insertion, DFT features, RTL design for DFT and verification.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Additional Locations

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.