Principal DFT Engineer

EnCharge AI; India; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

EnCharge AI is seeking a senior DFT Architect to lead the testing strategy for next-generation edge-to-cloud SoCs. You will define end-to-end DFT architecture, MBIST, IST, and POST methodologies, ensuring manufacturability and reliability in remote edge deployments.

Join a fast-moving hardware and software team and collaborate with Design, Physical Design, and Yield to maximize test coverage while minimizing area and power. 14–20 years of DFT experience required.

Qualifications

• 14–20 years of experience in DFT
• Experience in leadership/principal roles
• Strong knowledge of edge and data-center testing requirements

Responsibilities

• Architect end-to-end DFT for complex SoCs including hierarchical DFT, scan compression and MBIST
• Develop IST and POST strategies for edge deployments
• Oversee scan insertion, ATPG and Logic BIST
• Collaborate with Design, Physical Design and Yield teams to balance coverage, area and power
• Lead bring-up and debug on ATE to identify silicon failures and optimize test time

Skills

DFT expertise

Leadership

Edge/testing know-how

Tools

Synopsys TestMAX

Siemens Tessent

Cadence Modus

Job description

About Company:EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.

As the Design for Test (DFT) Architect, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.

Key Responsibilities

Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, and

MBIST.

Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.

Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Logic BIST.

Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact.

Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

Technical Requirements

Experience: 14-20 years in DFT, with at least 2 years in a leadership or principal role.

Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).

Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities and boundary scan (IEEE 1149.1/6).

Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).

Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.