Design Verification Manager

Texas Instruments; India; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Texas Instruments' RADAR product line is expanding in Industrial and automotive markets. As a Verification Engineer, you will own DV for IP, Subsystem and SoC, shaping verification methodologies and contributing to post-silicon sign-off.

You will collaborate with Architecture, RTL, PD, DFT, and analog teams; you will drive verification plans, TB development, and ensure ISO26262/ISO21434 compliance across programs.

Responsibilities

• Build, Mentor and scale high preforming verification team across IP, Subsystem and SoC level
• Lead verification activities for overall verification strategy, methodology, infrastructure and execution plans across multiple SoC programs.
• Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics.
• IP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.
• DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs
• Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities
• Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines
• Active involvement in the customer reviews and certifications (ISO26262/ISO21434).

Job description

The RADAR product line is a rapidly expanding business within TI, investing to address the fast-growing segment in Industrial & automotive markets. This product line will enable a scalable portfolio using DSP and ARM multi-cores to support high-end applications in ADAS, body & Chassis and in Industrial space.Radar systems process digital information from sources like digital cameras, lasers, radar and other sensors to perform tasks such as lane departure warning or parking assistance. The processed information can be displayed on screens or announced via acoustical warning signals. The system has multifaceted features such as Highprecision ADC, extremely accurate chirp, wide range visibility and Faster scene processing abilities. As a Verification Engineer, you will play a pivotal role in ensuring the quality and reliability of our advanced RADAR products. You will be responsible for the verification of IP, Subsystem (SS), and System-on-Chip (SoC) designs, contributing to the development of robust verification methodologies, strategies and team.

Responsibilities:

Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:

• Build, Mentor and scale high preforming verification team across IP, Subsystem and SoC level
• Lead verification activities for overall verification strategy, methodology, infrastructure and execution plans across multiple SoC programs.
• Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics.
• IP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.
• DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs
• Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities
• Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines
• Active involvement in the customer reviews and certifications (ISO26262/ISO21434).