Design Verification Lead

UANDWE, Inc.; Hyderabad; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

UANDWE, Inc. seeks an experienced DV verification engineer for SoC/subsystem verification in Hyderabad. You will define verification strategies, develop UVM testbenches, and drive coverage and assertion checks across SPI, UART, I2C, and audio interfaces while coordinating with RTL engineers.

The role requires 8+ years of DV experience, strong SystemVerilog/UVM skills, and AMBA protocol familiarity. The position is on-site in Hyderabad with potential for collaboration on post-silicon validation.

Qualifications

• 8+ years of DV experience in SoC/subsystem verification.
• Strong expertise in SystemVerilog and UVM.
• Experience verifying AMBA protocols (AXI/AHB/APB) and peripheral interfaces.

Responsibilities

• Define and execute verification strategy for subsystems: SPI, UART, I2C, Audio interfaces (I2S, TDM).
• Develop test plans with full functional and corner-case coverage.
• Identify verification risks and coverage gaps early.
• Build and maintain UVM/SystemVerilog testbenches: reusable VIPs, monitors, scoreboards, checkers, constrained-random stimulus.
• Ensure closure of coverage goals and assertion checks.
• Track and report verification metrics.
• Debug RTL issues and root-cause failures; collaborate with RTL engineers.

Skills

SystemVerilog

UVM

Functional coverage

Assertions

Debugging

Education

Bachelor's degree in Electrical Engineering or related field

Tools

AMS co-sim

AMBA protocols (AXI/AHB/APB)

Job description

Key Responsibilities: Min 8+ years experience required.

Define and execute verification strategy for subsystems: o SPI, UART, I2C o Audio interfaces (I2S, TDM) o Power management digital controllers

Develop test plans with full functional and corner-case coverage

Identify verification risks and coverage gaps early

UVM-Based Verification Development

Build and maintain UVM/System Verilog testbenches Develop: o Reusable VIPs and monitors o Scoreboards and checkers o Constrained-random stimulus

Ensure closure of: o Coverage goals o Assertion checks

Track and report verification metrics

Debug & Validation

Debug RTL issues and root-cause failures

Work closely with RTL engineers on bug fixes and improvements

Support post-silicon validation with test reuse where applicable

Contribute to SoC-level verification: o Subsystem integration scenarios o Firmware-driven tests Validate interactions across clock, reset, and power domains

Required Qualifications

8+years of DV experience in SoC/subsystem verification

Strong expertise in: o System Verilog and UVM o Functional coverage and assertions (SVA) Experience verifying: o AMBA protocols (AXI/AHB/APB) o Peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications

Experience with mixed-signal verification environments (AMS co-sim is a plus)

Exposure to low-power verification (UPF/CPF)

Familiarity with ARM Cortex-M33 or RISC-V SoCs