Design Verification Manager

118-WW TMG MFG OPS; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

118-WW TMG MFG OPS is seeking a Verification Manager to lead IP/SoC DV across RTL/PARTL and GLS/PAGLS with ISO 26262/21434 alignment. You will own DV strategy, test benches, UVC integration, and post-silicon closure, working with Architecture, RTL, PD, DFT, Systems, and Firmware teams.

The role requires 8–12 years in SoC or IP verification, strong scripting (Python/Perl), C-based DV experience, and familiarity with Cadence tools and safety standards. Excellent communication is essential.

Qualifications

• Bachelor's or Master's degree in EE/EC/EI/CS, or related specializations.
• 8–12 years of relevant experience.

Responsibilities

• End-to-End ownership of IP/subsystem/SOC DV/Post silicon debugs ownership from spec definition to post-silicon verification.
• Define verification strategy with traceability between specifications and regression.

Skills

UVM/SystemVerilog

Specman

GLS/PAGLS/UPF

Python

Perl

C-based DV

ARM systems

AI/ML DV

CAN I2C SPI UART USB

Cadence Xcelium

ISO 26262/21434

Cross-functional leadership

Education

Bachelor's/Master's EE/EC/CS

Tools

Cadence Xcelium

vManager

Formal JG tools

Job description

Change the world. Love your job.

The MSP design team, part of Embedded Processing (EP), develops cutting-edge system-on-chips (SoCs) that are affordable and ultra-low-power, featuring integrated high-performance digital and analog peripherals for a wide range of applications in the industrial, automotive, and embedded sectors. The team is responsible for architecting and developing differentiated intellectual properties (IPs) and SoCs that minimize power consumption while delivering superior analog and computing performance. The team’s responsibilities include designing low-power SoC architectures, hardware accelerators, safety and security infrastructure, and application-specific control and communication peripherals. They also oversee the integration of these IPs into SoCs, along with implementation, tape-out, and post-silicon release-to-market enablement.

As a Verification Manager, you will play a crucial role in ensuring the quality and reliability of our advanced MSP products. Your duties will include verifying IPs, SoC designs, and assisting with customer debugging, while also contributing to the development of robust verification methodologies and strategies in accordance with ISO 26262/ISO 21434 standards.

Responsibilities:

End-to-End ownership of IP/subsystem/SOC DV/Post silicon debugs ownership right from spec definition till the post silicon verification and solving the customer issues. This includes:

Technical:

• Actively collaborate with the architecture team during the specification definition phase.
• Define the verification strategy along with a plan to ensure 100% traceability between specifications and regression, including standard signoff metrics.
• Conduct IP, SubSystem, and SoC verification, covering both functional and firmware scenarios in RTL/PARTL and GLS/PAGLS modes.
• IP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.
• Own the DV environment, which includes defining and developing test benches, enhancing UVC integration, updating checkers and coverage monitors, and adapting the DV flow as needed for the project.
• Proficient in analog and mixed-signal (AMS) verification, clock domain crossing (CDC) digital verification, formal verification, and post-silicon verification.
• Work closely with cross-functional teams - including Architecture, RTL, PD, DFT, Systems, Analog, Firmware, and Application teams - to achieve verification goals for IP, subsystem, and SoC from specification definition through to post-silicon verification closure.
• Provide final SoC DV signoff based on regression results, coverage metrics, and DV to specification traceability using C and/or SV-UVM, while adhering to ISO 26262/ISO 21434 guidelines.
• Actively participate in customer reviews and certification processes (ISO 26262/ISO 21434).

Minimum requirements:

• Education: Bachelor's or Master's degree in EE/EC/EI/CS, or related specializations.
• Experience: A minimum of 8-12 years in relevant fields.

Preferred Skillset:

• Experience in C-based System-on-Chip (SoC) design verification (DV), with exposure to firmware verification and deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/UPF based verification, post-silicon verification, etc.
• Proficient in scripting languages such as Perl and Python, and knowledgeable in AI/ML-based DV.
• In-depth understanding of various standard protocols, including AHB, CAN, I2C, SPI, UART, USB.
• Work experience in a C-based environment involving ARM systems, particularly with power-aware simulations, is a significant advantage.
• Strong grasp of digital design fundamentals, computer organization and architecture, and bus protocols.
• Excellent debugging skills with Verilog and VHDL designs.
• Solid problem-solving abilities.
• Familiarity with Cadence tools (such as Xcelium, vManager, Formal JG applications, and safety simulators) or similar tools and DV flows.
• Demonstrate excellent verbal and written communication skills, enabling the development of strong relationships and seamless interaction with key internal and external stakeholders.
• Proven ability to manage, lead, and collaborate with cross-functional teams while taking the initiative to drive projects forward.
• Familiarity with functional safety and cybersecurity processes
• Proactively improve daily operations by keeping up with the latest technical trends and actively participating in both internal and external technology forums and conferences.
• Demonstrate strong interpersonal and analytical skills to effectively address complex problems and navigate organizational challenges.
• Quickly adapt to new systems and processes while managing time effectively to ensure on-time delivery.