Design Verification Faculty (Full-Time | Offline)

MOSart Labs; Hyderabad; On-site; INR 1,500,000 - 2,100,000; Full time

Benefits offered by this job

Competitive compensation package

Professional growth and leadership机会

Collaborative and innovation-driven工作氛

Job summary

MOSart Labs in Hyderabad (India) invites applications for a full-time Design Verification Faculty to deliver offline classroom training, supervise hands-on labs, mentor students, and guide project work. The role emphasizes industry-aligned design verification using SystemVerilog and UVM, with practical sessions and assessments to build placement readiness.

Candidates with semiconductor industry experience and a passion for teaching will be highly preferred.

Qualifications

• M.Tech / M.E. / M.S. in VLSI, Microelectronics, Electronics, or related field from a premier institute.
• Strong hands-on knowledge of SystemVerilog and UVM.

Responsibilities

• Deliver offline classroom training on Design Verification and Advanced Design Verification.
• Conduct hands-on lab sessions using industry-standard EDA tools.
• Develop course content, lab manuals, assignments, and verification projects.
• Mentor students on Design Verification projects, internships, and placements.
• Evaluate student performance and provide technical guidance.
• Lead practical coding, simulation, debugging, and verification sessions.
• Guide students in SystemVerilog and UVM-based verification environments.
• Stay updated with latest verification methodologies and EDA tools.

Skills

SystemVerilog

UVM

Design Verification

Teaching and mentoring

Lab facilitation

Communication

Education

M.Tech / M.E. / M.S. in VLSI or related field

Strong hands-on SystemVerilog & UVM

Tools

Synopsys VCS

Cadence Xcelium

Cadence SimVision

Job description

This is a full-time teaching and faculty role. The selected candidate will be responsible for classroom training, hands-on lab sessions, student mentoring, project guidance, assessments, and placement preparation.

Candidates with strong semiconductor industry experience who are passionate about teaching and mentoring students will be highly preferred.

About MOSart Labs

MOSart Labs is a leading Semiconductor Training & Chip Design company committed to building industry-ready VLSI engineers through hands-on, industry-focused training. We are looking for a passionate and experienced Design Verification Faculty to deliver high-quality corporate-level offline classroom training and mentor aspiring Design Verification Engineers.

Key Responsibilities

• Deliver offline classroom training on Design Verification and Advanced Design Verification.
• Conduct hands-on laboratory sessions using industry-standard EDA tools.
• Develop course content, lab manuals, assignments, assessments, and verification projects.
• Mentor students on Design Verification projects, internships, and placement preparation.
• Evaluate student performance and provide technical guidance.
• Conduct practical coding, simulation, debugging, and verification sessions.
• Guide students in developing industry-oriented SystemVerilog and UVM-based verification environments.
• Stay updated with the latest semiconductor verification methodologies, technologies, protocols, and EDA tools.
• Collaborate with internal technical teams to continuously enhance the Design Verification curriculum.

Required Technical Skills

• Strong understanding of ASIC/IP/SoC Design Verification.
• SystemVerilog Fundamentals
• Constrained Random Verification
• Functional Coverage
• SystemVerilog Assertions (SVA)
• Scoreboards & Drivers
• Verification Planning and Flow
• Verification IP (VIP)
• Coverage Closure
• Assertion-Based Verification
• Analog/Mixed-Signal Verification

EDA Tool Experience

Hands-on experience with one or more of the following:

• Synopsys VCS
• Cadence Xcelium
• Cadence SimVision
• Other industry-standard Design Verification tools

Protocol Experience – Preferred

Experience with one or more of the following:

• AMBA AXI / AXI4
• AHB
• DDR
• Ethernet
• USB
• SPI / I2C / UART

Qualification

Mandatory

• M.Tech / M.E. / M.S. in VLSI, Microelectronics, Electronics, or a related specialization from a reputed institute (IITs, NITs, IIITs, Central Universities, or other premier institutions).
• Strong hands-on knowledge of SystemVerilog and UVM.

Preferred

• Ph.D. in VLSI, Semiconductor Engineering, or a related field.
• Prior teaching, mentoring, faculty, or corporate training experience.
• Candidates with semiconductor industry experience will be given preference.
• Experience in complex ASIC/IP/SoC verification projects is an added advantage.

Experience

• 5–10 years of relevant experience in ASIC/IP/SoC Design Verification.
• Strong hands-on industry experience in SystemVerilog and UVM.
• Prior teaching, mentoring, or corporate training experience is preferred.
• Experience working on complex verification projects and advanced protocols is an added advantage.

Required Skills

• Excellent communication and presentation skills.
• Strong mentoring and classroom management abilities.
• Strong practical knowledge of SystemVerilog and UVM.
• Passion for teaching and developing future semiconductor professionals.
• Ability to simplify complex verification concepts through practical demonstrations.
• Ability to conduct interactive classroom and hands-on laboratory sessions.
• Strong debugging and problem‑solving skills.

What We Offer

• Opportunity to work with a fast-growing Semiconductor Training & Chip Design organization.
• Opportunity to train students using industry-standard Design Verification methodologies and EDA tools.
• Exposure to real‑world verification flows and project‑based training.
• Competitive compensation package.
• Professional growth and technical leadership opportunities.
• Collaborative and innovation-driven work environment.