Design Verification Engineer, Silicon Engineering

Google LLC; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Google LLC's Silicon Engineering team is seeking a Design Verification Engineer to help verify next-generation custom silicon accelerators and SoCs. You will build UVM-based test environments, write SystemVerilog constraints, and collaborate with design, architecture, and emulation teams to ensure production-grade silicon.

The role requires a Bachelor's in a relevant field or equivalent experience, 4 years of RTL verification with SystemVerilog, and UVM expertise.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practice.
• 4 years of RTL verification experience using SystemVerilog for FPGAs/ASICs.
• Experience with UVM testbenches/environments.

Responsibilities

• Create and improve constrained-random verification environments using SystemVerilog and UVM.
• Use SystemVerilog Assertions (SVA) and formal tools for formal verification.
• Perform power-aware simulations and formal verification to validate power management features.
• Develop and execute coverage-driven verification plans and collaborate with design engineers.

Skills

RTL verification

SystemVerilog

UVM

FPGAs/ASICs

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

UVM

SystemVerilog Assertions (SVA)

Job description

Design Verification Engineer, Silicon Engineering

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience verifying digital logic at RTL using System Verilog for FPGAs and ASICs.
  
• Experience with UVM Testbenches/environments.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Expertise in creating/using verification components and environments in UVM methodology at IP or Subsystem level.
• Experience with image processing, computer vision or machine learning IPs.
• Experience with AMBA(APB/AXI/ACE) or other standard protocols.
• Familiarity with CPU, GPU or other compute/ML architectures.
• Excellent communication and collaboration skills with the ability to work with cross-functional teams.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As an ASIC Design Verification Engineer on the Silicon team, you will verify next-generation custom silicon accelerators and SoCs, build advanced Universal Verification Methodology (UVM) test environments, and collaborate across design, architecture, and emulation teams to deliver production-quality silicon.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Create and improve constrained-random verification environments using SystemVerilog and UVM. Use SystemVerilog Assertions (SVA) and formal tools for formal verification.
• Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and Dynamic Voltage and Frequency Scaling (DVFS). Develop and implement power-aware test cases, including stress and corner-case scenarios, for robust power integrity.
• Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality.
• Plan the verification of complex digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.