Design Verification Engineer

Weekday; Bengaluru; On-site; INR 1,500,000 - 2,400,000; Full time

Job summary

Weekday is seeking an experienced Design Verification Engineer in Bengaluru to lead verification for ASIC/SoC blocks. You will develop verification plans, build UVM environments, and create reusable components to ensure correctness of DDR interfaces and memory subsystems.

The role requires 5–8 years in design verification, strong DDR and UVM/SystemVerilog skills, and hands-on testing with major simulators. Full-time position based in Bengaluru with client-facing responsibilities.

Qualifications

• 5-8 years of hands-on experience in design verification for ASIC/SoC.
• Strong expertise in DDR protocols and memory subsystem verification.
• Hands-on experience with UVM and SystemVerilog.
• Experience with constrained-random verification environments and reusable components.
• Familiarity with simulation and debugging tools (VCS/Xcelium/Questa).

Responsibilities

• Develop and execute comprehensive design verification plans for complex ASIC/SoC blocks.
• Design, develop, and maintain UVM-based verification environments using SystemVerilog.
• Build reusable UVM components including agents, drivers, monitors, sequencers, scoreboards, reference models, and coverage models.
• Develop constrained-random and directed test cases to validate functional, corner-case, and error scenarios.
• Verify DDR interfaces and memory controller designs, including timing, initialization, and data integrity.
• Analyze DDR protocol transactions and debug failures across simulators.
• Track verification progress, coverage, bugs, and regression results.

Skills

Design Verification

DDR protocols

UVM

SystemVerilog

Education

Electrical Engineering

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

This role is for one of Weekday's clients
Salary range: Rs 1500000 - Rs 2400000 (ie INR 15 - 24 LPA)

Min Experience: 5+ years
Location: Bengaluru, Karnataka, India
JobType: full-time

We are seeking an experienced Design Verification Engineer with 5-8 years of hands-on experience in ASIC/SoC verification, with strong expertise in DDR memory interfaces and UVM-based verification environments. The ideal candidate will be responsible for developing robust verification strategies, building reusable verification components, creating comprehensive test scenarios, and ensuring the functional correctness and reliability of complex digital designs.

You will work closely with RTL design, architecture, firmware, and validation teams to identify design issues early, improve verification coverage, and deliver high-quality silicon-ready designs.

Requirements

Key Responsibilities

• Develop and execute comprehensive design verification plans for complex ASIC/SoC blocks and subsystems.
• Design, develop, and maintain UVM-based verification environments using SystemVerilog.
• Build reusable UVM components including agents, drivers, monitors, sequencers, scoreboards, reference models, and coverage models.
• Develop constrained-random and directed test cases to validate functional, corner-case, and error scenarios.
• Perform verification of DDR interfaces and memory controller-related designs, including protocol behavior, initialization, timing, configuration, and data integrity.
• Analyze DDR protocol transactions, identify functional issues, and debug failures across simulation environments.
• Develop assertions and functional coverage to achieve comprehensive verification closure.
• Integrate verification environments with different IPs and SoC-level environments.
• Debug simulation failures using waveform analysis and industry-standard simulation/debug tools.
• Perform root-cause analysis of RTL, testbench, and specification issues and work closely with design teams to resolve them.
• Track verification progress, coverage metrics, bugs, and regression results.
• Participate in design and verification reviews and contribute to improving verification methodologies and automation.

Must-Have Skills

• 5-8 years of hands-on experience in Design Verification for ASIC, SoC, or complex digital designs.
• Strong expertise in DDR protocols and DDR-based memory subsystem verification.
• Strong hands-on experience with UVM (Universal Verification Methodology).
• Excellent programming experience in SystemVerilog.
• Strong understanding of UVM architecture and methodology, including sequences, sequencers, drivers, monitors, agents, scoreboards, configuration mechanisms, and factory concepts.
• Experience developing constrained-random verification environments and reusable verification components.
• Strong knowledge of functional coverage, code coverage, assertions, and coverage-driven verification.
• Experience with simulation and debug tools such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
• Strong understanding of digital design concepts, RTL, and Verilog/SystemVerilog.
• Hands-on experience with regression management, debugging, and verification sign-off.

Good-to-Have Skills

• Experience with DDR3, DDR4, DDR5, LPDDR4, or LPDDR5.
• Knowledge of memory controllers, PHY interfaces, initialization sequences, and timing-related scenarios.
• Experience with SVA (SystemVerilog Assertions) and formal verification concepts.
• Familiarity with scripting languages such as Python, Perl, or Tcl for verification automation.
• Experience with SoC-level verification and subsystem integration.
• Exposure to AMBA protocols such as AXI, APB, or AHB.
• Experience working with complex IP blocks and multi-clock/multi-reset environments.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Strong analytical, debugging, and problem-solving skills.
• Ability to work effectively with cross-functional engineering teams.
• Strong communication skills and attention to detail.

What You'll Bring

The ideal candidate combines deep DDR verification expertise with strong UVM/SystemVerilog proficiency and a systematic approach to verification. You should be comfortable working on complex designs, debugging difficult failures, improving verification infrastructure, and driving projects toward complete functional and coverage closure.