Design for Test (DFT) Engineer

Broadcom; Bengaluru; On-site; INR 4,000,000 - 8,000,000; Full time

Job summary

Broadcom in Bengaluru, India seeks a Senior DFT Engineer to lead advanced DFT implementations across MBIST and scan insertion, and to drive ATPG and pattern simulations. You will partner with design, verification, and ATE teams to ensure robust silicon bring-up and yield improvements.

Ideal candidates will have strong RTL lint experience, proficiency with Mentor Tessent and Synopsys DFT tools, and excellent communication skills for cross-functional collaboration.

Qualifications

• Bachelors in Engineering with 8+ years of related experience or Masters with 6+ years.
• Experience in silicon bring-up and yield improvement required.
• Solid understanding of DFT techniques and RTL lint checking.
• Proficiency with scan compression/insertion and ATPG.

Responsibilities

• Collaborate with ATE engineer on yield improvement and analysis.
• Develop ATE patterns and manage hand-off, including silicon debugging.
• Contribute to block and chip-level DFT implementation and testing.
• Work on DFT lint, MBIST architecture, and scan insertion using industry tools.
• Perform ATPG and pattern simulation for MBIST and scan.
• Coordinate with design, verification, and implementation teams during DFT phase.

Skills

DFT techniques

MBIST architecture

Scan insertion

ATPG

RTL lint

Perl scripting

Mentor Tessent

Synopsys tools

Silicon bring-up

Yield improvement

Debugging

Communication

Education

Bachelor's in Engineering

Master's degree

Tools

Mentor Tessent

Synopsys DFT tools

Job description

Job Description

As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.

Key Responsibilities

• Work closely with the ATE engineer on yield improvement and analysis.
• Develop ATE patterns, manage the hand-off process, and perform silicon debugging.
• Participate in block and chip-level DFT implementation, developing and executing all related tasks.
• Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.
• Perform ATPG and pattern simulation for both MBIST and scan.
• Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.
• Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology.

Required Qualifications

• Bachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of related experience
• Required experience in silicon bring-up and yield improvement.
• Solid understanding of DFT techniques.
• Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.
• Experience in MBIST architecture and insertion.
• Experience in analyzing and debugging simulation failures.
• Solid understanding of digital logic fundamentals.
• Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.
• Proficiency with Perl or other scripting languages.
• Strong communication and interpersonal skills.

Plus

• Experience in STA constraint development in DFT modes.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Experience Level Senior Level