DFT Engineer

Broadcom, Inc.; India; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Broadcom, Inc. in Bangalore, India is seeking an experienced DFT Engineer to own and drive DFT implementation, MBIST, and ATPG across block and chip levels. You will collaborate with design, verification, and ATE teams during silicon bring-up, develop patterns, and perform yield analysis.

The role requires 8+ years of related experience, strong RTL lint and debugging skills, proficiency with Mentor Tessent or Synopsys DFT tools, and scripting (Perl).

Qualifications

• Bachelor's degree in Engineering or higher required.
• 8+ years of related experience or 6+ years with Master's.

Responsibilities

• Work on DFT, MBIST, and scan insertion across block and chip level.
• Develop ATE patterns and assist silicon debugging.
• Collaborate with design, verification, and implementation teams during DFT design phase.
• Engage with cross-functional teams to refine DFT methodologies.
• Perform DFT lint checks and ATPG pattern simulations for MBIST and scan.

Skills

DFT techniques

RTL lint checking

Scan insertion

ATPG

MBIST architecture

Perl scripting

Debugging simulations

Digital logic fundamentals

Education

Bachelor's in Engineering

Master's degree in Engineering

Tools

Mentor Tessent

Synopsys DFT tools

ATPG tools

Simulation toolbox

Job description

DFT Engineer### DFT EngineerApply: IND-Bangalore Electronic City - S1: Full time: Posted Yesterday: R027594**Please Note:****1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)****2. If you already have a Candidate Account, please Sign-In before you apply.**## **Job Description:** As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.**Key Responsibilities**:* Work closely with the ATE engineer on yield improvement and analysis.* Develop ATE patterns, manage the hand-off process, and perform silicon debugging.* Participate in block and chip-level DFT implementation, developing and executing all related tasks.* Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.* Perform ATPG and pattern simulation for both MBIST and scan.* Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.* Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology.**Required Qualifications:*** Bachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of related experience* Required experience in silicon bring-up and yield improvement.* Solid understanding of DFT techniques.* Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.* Experience in MBIST architecture and insertion.* Experience in analyzing and debugging simulation failures.* Solid understanding of digital logic fundamentals.* Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.* Proficiency with Perl or other scripting languages.* Strong communication and interpersonal skills.* Plus: Experience in STA constraint development in DFT modes**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.****If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.**