Design-For-Test (DFT) Engineer

Accenture; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Accenture is seeking a Design-For-Test Engineer to embed testability features into chip designs, enabling efficient post-manufacturing testing. You will collaborate with design and verification teams to optimize for test coverage and fault isolation, ensuring high silicon quality and reliability.

The role emphasizes deep DFT knowledge, scan chain insertion, BIST architectures, and boundary scan techniques. Minimum 3 years of experience and 15 years of full-time education are required, with

Qualifications

• Must have Design for Testability (DFT).
• Minimum 3 years of experience in DFT.
• Knowledge of scan chain insertion, BIST and boundary scan.

Responsibilities

• Perform independently and become an SME.
• Active participation in team discussions.
• Contribute in providing solutions to work related problems.
• Collaborate with cross-functional teams to integrate test features into design workflows.
• Analyze test results and provide feedback to improve design for testability.
• Support junior team members by sharing knowledge.
• Continuously update test methodologies to keep pace with evolving design challenges.

Skills

DFT

Scan chain insertion

BIST architectures

Boundary scan

Fault isolation

Testability collaboration

Education

15 years full time education

Job description

Project Role :

Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.

Must have skills : Design for Testability (DFT)

Good to have skills : NA

Minimum 3 year(s) of experience is required

Educational Qualification : 15 years full time education

Summary:

As a Design-For-Test Engineer, a typical day involves embedding testability features into chip designs to facilitate efficient testing after manufacturing. This role requires close collaboration with design and verification teams to ensure that the integrated test mechanisms effectively identify defects and improve overall test coverage. The engineer focuses on optimizing the design to support fault isolation and enhance the quality of the silicon product, ensuring that the final output meets rigorous standards for reliability and performance.

Roles & Responsibilities:

• Expected to perform independently and become an SME.
• Required active participation/contribution in team discussions.
• Contribute in providing solutions to work related problems.
• Collaborate with cross-functional teams to integrate test features seamlessly into design workflows.
• Analyze test results and provide feedback to improve design for enhanced testability.
• Support junior team members by sharing knowledge and assisting in problem-solving.
• Continuously update and refine test methodologies to keep pace with evolving design challenges.

Professional & Technical Skills:

• Must To Have Skills: Proficiency in Design for Testability (DFT).
• Experience with scan chain insertion and optimization techniques.
• Familiarity with Built-In Self-Test (BIST) architectures and implementation.
• Knowledge of boundary scan standards and their application in chip testing.
• Ability to collaborate effectively with design and verification teams to enhance test coverage.
• Strong problem-solving skills related to fault isolation and test efficiency.

Additional Information:

• The candidate should have minimum 3 years of experience in Design for Testability (DFT).
• This position is based at our BDC6F - SEZ location.
• A 15 years full time education is required.

15 years full time education

Equal Employment Opportunity Statement

All employment decisions shall be made without regard to age, race, creed, color, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.

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