Design For Testability DFT - Engineer

Nsemi Design Services India Pvt Ltd

Bengaluru

On-site

INR 1,500,000 - 2,300,000

Full time

14 days+

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Job summary

Nsemi Design Services India Pvt Ltd is seeking a DFT Engineer to design and implement Design-for-Test strategies for high-quality semiconductor products. You will apply scan insertion, ATPG, and MBIST to optimize test coverage and silicon debug processes, collaborating with cross‑functional teams on robust test solutions.

The role requires 3+ years of DFT experience on complex SoCs, a degree in Electronics/ Electrical/ Telecom/ VLSI, and hands-on expertise with Cad tools such as Tetramax and

Qualifications

3+ years of experience in DFT on high complexity SoC designs.
Bachelors OR Masters in Electronics, Electrical, Telecom or VLSI Engineering.

Responsibilities

3+ Experience in complex SOC level DFT execution in advanced finFET technology.
Strong DFT fundamental knowledge from defect models to ATPG algorithm.
Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.
Knowledge of basic SoC architecture and HDL languages like Verilog to work with design teams for timing fixes

Skills

DFT

ATPG

MBIST

Scan insertion

Verilog HDL

SoC architecture

Communication

Presentation skills

Ownership

Creative problem solving

Education

Bachelor's or Master's in Electronics/Electrical/Telecom/VLSI

Tools

Synopsys Tetramax

Mentor Tessent

Job description

As a DFT Engineer at Nsemi, you will be responsible for designing and implementing Design-for-Test strategies to ensure the highest quality and reliability of our semiconductor products. Your expertise in scan insertion, ATPG, and MBIST will be crucial in optimizing test coverage and enhancing silicon debug processes. You’ll collaborate closely with cross‑functional teams to deliver robust and efficient test solutions, playing a vital role in the success of our cutting‑edge projects.

Design For Testability DFT - Engineer

Qualification Required

Typically requires minimum of 3+ years of experience in DFT on high complexity SoC designs.
Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.
Typically requires minimum of 3+ years of experience in DFT on high complexity SoC designs.
Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Roles And Responsibilities

3+ Experience in complex SOC level DFT execution in advanced finFET technology.
Strong DFT fundamental knowledge from defect models to ATPG algorithm.
Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.
Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes
3+ Experience in complex SOC level DFT execution in advanced finFET technology.
Strong DFT fundamental knowledge from defect models to ATPG algorithm.
Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.
Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes

Required Technical And Professional Expertise

Excellent communication and interpersonal skills.
Strong and effective presentation skills, able to operate at multiple levels including senior management.
Self-motivated.
Take ownership of problems.
Creative problem solving.
Team player
Excellent communication and interpersonal skills.
Strong and effective presentation skills, able to operate at multiple levels including senior management.
Self-motivated.
Take ownership of problems.
Creative problem solving.
Team player