Design-For-Test (DFT) Engineer

Accenture in India; Bengaluru; On-site; INR 2,000,000 - 2,800,000; Full time

Job summary

Accenture in India is seeking a Design-For-Test Engineer based in Bengaluru to drive post-manufacturing testability enhancements during the design phase. You will apply DFT methodologies to improve test efficiency and fault isolation, collaborating with design and verification teams to ensure high-quality silicon.

The role emphasizes SME-level DFT expertise, leadership of the DFT team, and interaction with multiple groups to deliver robust test solutions and effective coverage.

Qualifications

• Must have 7.5 years of experience in Design for Testability (DFT).
• Strong understanding of DFT principles and methodologies.
• Experience with scan chains, BIST, and boundary scan is required or highly preferred.

Responsibilities

• Act as SME for DFT and related test methodologies.
• Collaborate with design and verification teams to guide DFT implementations.
• Lead and manage the DFT team in evaluating and applying test strategies.
• Engage with multiple teams to influence design decisions.
• Develop and implement innovative DFT strategies to enhance test coverage.
• Review design specifications to ensure compliance with DFT standards.

Skills

DFT

Scan chain design

BIST

Boundary scan

Education

15 years full time education

Job description

Project Role : Design-For-Test (DFT) Engineer

Project Role Description : Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.

Must have skills : Design for Testability (DFT)

Good to have skills : NA

Minimum 7.5 Year(s) Of Experience Is Required

Educational Qualification : 15 years full time education

Summary: As a Design-For-Test Engineer, you will enable effective post-manufacturing chip testing by integrating testability features during the design phase. Your typical day will involve collaborating with various teams to apply DFT methodologies, ensuring that the designs are optimized for test efficiency and fault isolation, ultimately contributing to the production of high-quality silicon.

Roles & Responsibilities:

• Expected to be an SME.
• Collaborate and manage the team to perform.
• Responsible for team decisions.
• Engage with multiple teams and contribute on key decisions.
• Provide solutions to problems for their immediate team and across multiple teams.
• Develop and implement innovative DFT strategies to enhance test coverage.
• Conduct regular reviews of design specifications to ensure compliance with DFT standards.

Professional & Technical Skills:

• Must To Have Skills: Proficiency in Design for Testability (DFT).
• Strong understanding of scan chain design and implementation.
• Experience with Built-In Self-Test (BIST) methodologies.
• Familiarity with boundary scan techniques and tools.
• Ability to analyze and troubleshoot test coverage issues.

Additional Information:

• The candidate should have minimum 7.5 years of experience in Design for Testability (DFT).
• This position is based at our Bengaluru office.
• A 15 years full time education is required.