Design Engineer

Proxelera; Bengaluru; On-site; INR 600,000 - 900,000; Full time

Job summary

Proxelera seeks a Junior Analog/Mixed-Signal Design Engineer to validate transistor-level variability for crypto subsystems, porting designs to silicon and ensuring entropy and reliability assumptions hold on real devices.

You will run Monte Carlo analyses, develop SPICE testbenches, and translate results into architectural insights, collaborating with the PUF architect and digital teams.

Qualifications

• Solid grounding in CMOS device physics and process variation concepts.
• Familiarity with reading and modifying SPICE netlists.

Responsibilities

• Set up Monte Carlo mismatch simulations with SPICE (HSPICE/PrimeSim) across circuit structures.
• Build and maintain SPICE testbenches for transistor-level layouts.
• Characterize device- and cell-level variability and translate results to entropy/bit-error-rate estimates.
• Support layout-matching strategies for controlled mismatch in designs.
• Validate PDK MC model decks and verify proper variation separation for downstream use.
• Assist silicon characterization plans (PVT sweeps, corner analysis).

Skills

Python scripting

CMOS device physics

SPICE netlists reading

Circuit-level analysis

Education

BE in ECE

ME/MS in Microelectronics

Tools

HSPICE

PrimeSim

Spectre

Custom Design tools (PM/PC)

Job description

Analog / Mixed-Signal Design Engineer

Device & Variability Characterization

Team: Crypto / Security IP
Reports to: PUF Architect
Level: Junior (03 years post-degree, or strong new-grad with relevant internship/research experience)

About the Role

We are developing critical transistor characteristic dependant circuits for our crypto subsystem, currently being ported from GF 22FDX to TSMC 12FFC. This requires SPICE-level work to validate that the digital architecture's entropy and reliability assumptions actually hold on real silicon.
You'll work directly with the PUF designer, translating architectural requirements into concrete circuit-level simulation, and feeding real numbers back into the architecture (frequency estimates, counter sizing, error budgets, weak-bit thresholds).

What You'll Do

• Set up and run Monte Carlo mismatch simulations (Synopsys HSPICE / PrimeSim) on circuit structures, separating local (mismatch) from global (process corner) variation sources.
• Build and maintain SPICE testbenches for standard-cell-based circuits at the transistor level, matching RTL/gate-level structures exactly.
• Characterize device- and cell-level variability (RDF, LER, work-function variation) on TSMC 12FFC and translate results into entropy, uniqueness, and bit-error-rate estimates the digital architecture depends on.
• Support layout-level matching strategy (common-centroid, interdigitation, dummy device placement) for circuits where mismatch is the intended signal.
• Bring up and validate PDK statistical/MC model decks with the foundry confirm global/local variation separation is modeled correctly before results are trusted downstream.
• Help design and execute silicon characterization/validation plans (PVT sweeps, corner analysis) once test chips are available.
• Document simulation methodology and results clearly enough that a primarily-digital architect can act on them without needing to be an analog expert themselves.

Required Qualifications

• BE in ECE, or ME/MS in Microelectronics (MS a plus, not required).
• Working knowledge of SPICE-level circuit simulation (HSPICE, PrimeSim, Spectre, or similar) lab/internship experience is sufficient; this does not need to be professional experience.
• Solid grounding in CMOS device physics and understanding of device mismatch/process variation as a concept (why two "identical" transistors aren't identical).
• Comfortable reading and modifying SPICE netlists and interpreting PDK documentation.
• Basic scripting ability (Python preferred) for simulation automation and post-processing.
• Clear written communication this role sits at the interface between analog circuit work and a digital architecture team, and the ability to explain results plainly matters as much as the simulation work itself.

Preferred (Not Required)

• Exposure to FinFET-specific device behavior (vs. planar/FD-SOI)
• Familiarity with statistical/Monte Carlo methods, including at least conceptual awareness of rare-event/high-sigma techniques (e.g., importance sampling) beyond brute-force MC.
• Any exposure to PUF, TRNG, or other variation-exploiting security IP genuinely rare to find in a junior candidate, a strong plus if present but not expected.
• Analog/mixed-signal layout experience, especially matching techniques for differential structures.
• Experience with Synopsys Custom Design Platform (PrimeWave, Custom Compiler) specifically.