Analog/Mixed signal engineer

Proxelera; Bengaluru; On-site; INR 900,000 - 1,400,000; Full time

Job summary

Proxelera in Bengaluru, India is seeking a motivated engineer to perform SPICE‑level circuit validation for a crypto subsystem ported to TSMC 12FFC. You’ll translate architectural needs into transistor‑level simulations and feed real numbers back into the architecture.

Work directly with the PUF designer to quantify entropy, uniqueness and error budgets, build SPICE testbenches, run Monte Carlo analyses, and document results for the digital team.

Qualifications

• BE in ECE; ME/MS in Microelectronics is a plus
• Working knowledge of SPICE-level circuit simulation (lab/internship acceptable)
• Solid grounding in CMOS device physics and variation concepts
• Able to read/modify SPICE netlists and interpret PDK docs
• Basic scripting for automation (Python preferred)
• Clear written communication at interface between analog and digital teams

Responsibilities

• Run Monte Carlo mismatch simulations (HSPICE/PrimeSim) on circuit structures, separating local vs global variation
• Build and maintain SPICE testbenches for transistor-level circuits
• Characterize device- and cell-level variability and translate results into entropy, uniqueness, and BER estimates
• Support layout matching strategies for circuits where mismatch is the signal
• Validate PDK statistical/MC models with foundry data
• Design silicon characterization plans (PVT sweeps, corner analysis) for test chips
• Document methodology and results for a primarily-digital architect to act on

Skills

SPICE Simulation

CMOS Device Physics

Variation & Mismatch

SPICE Netlists

Python Scripting

Technical Communication

Education

BE in ECE

ME/MS in Microelectronics

Tools

HSPICE/PrimeSim/Spectre

Job description

About the Role

We are developing critical transistor characteristic dependant circuits for our crypto subsystem, currently being ported from GF 22FDX to TSMC 12FFC. This requires SPICE-level work to validate that the digital architecture's entropy and reliability assumptions actually hold on real silicon.

You’ll work directly with the PUF designer, translating architectural requirements into concrete circuit-level simulation, and feeding real numbers back into the architecture (frequency estimates, counter sizing, error budgets, weak-bit thresholds).

What You'll Do

• Set up and run Monte Carlo mismatch simulations (Synopsys HSPICE / PrimeSim) on circuit structures, separating local (mismatch) from global (process corner) variation sources.
• Build and maintain SPICE testbenches for standard-cell-based circuits at the transistor level, matching RTL/gate-level structures exactly.
• Characterize device- and cell-level variability (RDF, LER, work‑function variation) on TSMC 12FFC and translate results into entropy, uniqueness, and bit-error-rate estimates the digital architecture depends on.
• Support layout‑level matching strategy (common-centroid, interdigitation, dummy device placement) for circuits where mismatch is the intended signal.
• Bring up and validate PDK statistical/MC model decks with the foundry confirm global/local variation separation is modeled correctly before results are trusted downstream.
• Help design and execute silicon characterization/validation plans (PVT sweeps, corner analysis) once test chips are available.
• Document simulation methodology and results clearly enough that a primarily-digital architect can act on them without needing to be an analog expert themselves.

Required Qualifications

• BE in ECE, or ME/MS in Microelectronics (MS a plus, not required).
• Working knowledge of SPICE-level circuit simulation (HSPICE, PrimeSim, Spectre, or similar) —lab/internship experience is sufficient; this does not need to be professional experience.
• Solid grounding in CMOS device physics and understanding of device mismatch/process variation as a concept (why two "identical" transistors aren't identical).
• Comfortable reading and modifying SPICE netlists and interpreting PDK documentation.
• Basic scripting ability (Python preferred) for simulation automation and post-processing.
• Clear written communication — this role sits at the interface between analog circuit work and a digital architecture team, and the ability to explain results plainly matters as much as the simulation work itself.

Preferred candidate profile

Perks and benefits