Delivery Manager II

UST; Bengaluru; On-site; INR 3,500,000 - 7,500,000; Full time

Job summary

UST is seeking a seasoned Delivery Manager II to lead and scale its Design Verification practice. You will own the DV portfolio, set strategy, and collaborate with sales, account managers, and delivery leaders to drive growth across ASIC, SoC, IP, and subsystem verification engagements.

The role blends deep technical verification expertise with business acumen to build a differentiated, trusted partner for global semiconductor customers, delivering high-impact solutions and guiding capability

Qualifications

• Leadership of DV practice with P&L ownership is expected.

Responsibilities

• Own DV practice P&L, revenue, margins, and growth targets.
• Develop and execute a 3-year practice growth strategy.
• Work with sales, account managers, and delivery leaders to identify opportunities.
• Participate in customer meetings, solution discussions, and RFP/RFQ responses.
• Build strategic relationships with semiconductor customers globally.
• Drive mining of existing accounts and acquisition of new logos.
• KPIs: Revenue growth, New customer acquisitions, Pipeline generation, Conversion rate and Gross margin.
• Ensure successful execution of DV projects.

Skills

Delivery leadership

Business development

Customer engagement

Strategic planning

People management

Tools

UVM

SystemVerilog

ABV

UPF

PCIe

MIPI

AMBA AXI

Job description

Who We Are

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

Role Description

UST Title- Delivery Manager II

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

Summary

The Practice Head – Design Verification (DV) will lead and scale UST's Design Verification practice by driving business growth, delivery excellence, capability development, talent strategy, and customer success across ASIC, SoC, IP, and subsystem verification engagements. This leadership role combines deep technical expertise with strong business acumen to build a differentiated verification practice and establish UST as a trusted partner for global semiconductor customers.

The Opportunity

UST is looking for a Practice Head – Design Verification (DV) to build, scale, and lead its Design Verification practice. The ideal candidate will own the practice strategy, P&L, customer engagement, solution development, and organizational growth while driving innovation and delivery excellence across semiconductor verification services.

Key Roles & Responsibilities

• Practice Growth & Business Development
  • Own DV practice P&L, revenue, margins, and growth targets.
  • Develop and execute a 3-year practice growth strategy.
  • Work closely with sales, account managers, and delivery leaders to identify and pursue opportunities.
  • Participate in customer meetings, solution discussions, and RFP/RFQ responses.
  • Build strategic relationships with semiconductor customers globally.
  • Drive mining of existing accounts and acquisition of new logos.
  • KPIs: Revenue growth, New customer acquisitions, Pipeline generation, Conversion rate and Gross margin.
• Capability Building
  • Define And Build Capabilities In
    • Functional Verification
    • UVM
    • SystemVerilog
    • Assertion-Based Verification (ABV)
    • Coverage-Driven Verification
    • Advanced Verification
    • Formal Verification
    • Emulation
    • FPGA Prototyping
    • Portable Stimulus
    • SoC Verification
    • Subsystem Verification
    • Integration Verification
    • Performance Verification
    • Low Power Verification (UPF)
    • Protocol Expertise
    • PCIe
    • USB
    • Ethernet
    • DDR
    • MIPI
    • CXL
    • UCIe
    • AMBA AXI/AHB/APB
    • AMS Verification
    • Mixed Signal Verification
    • Real Number Modeling
    • KPIs
    • Number of certified engineers
    • New capability launches
    • Reusable verification IPs developed
• Delivery Excellence
  • Ensure successful execution of all DV projects.