Design Verification Manager

Texas Instruments; India; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Texas Instruments in India is seeking a Verification Manager to own IP/subsystem/SoC DV from specification through post-silicon verification and to support customer debugging. You will define and drive verification strategies, ensure traceability between specs and regressions, and work with Architecture, RTL, DFT, and firmware teams to meet challenging milestones.

The role requires deep expertise in AMS, CDC, formal verification, and SV-UVM, with a focus on ISO 26262/ISO 21434.

Qualifications

• End-to-end IP/SoC DV ownership from spec through post-silicon verification.
• Define verification strategy and ensure 100% traceability between specs and regression.
• Collaborate with Architecture, RTL, PD, DFT, Systems, Analog, Firmware, and Applications teams.

Responsibilities

• End-to-End ownership of IP/subsystem/SoC DV/Post silicon debugs ownership right from spec definition till the post silicon verification and solving the customer issues.
• Define the verification strategy along with a plan to ensure 100% traceability between specifications and regression, including standard signoff metrics.
• Conduct IP, SubSystem, and SoC verification, covering both functional and firmware scenarios in RTL/PARTL and GLS/PAGLS modes.
• Own the DV environment, which includes defining and developing test benches, enhancing UVC integration, updating checkers and coverage monitors, and adapting the DV flow as needed for the project.
• Proficient in analog and mixed-signal (AMS) verification, clock domain crossing (CDC) digital verification, formal verification, and post-silicon verification.
• Work closely with cross-functional teams - including Architecture, RTL, PD, DFT, Systems, Analog, Firmware, and Application teams - to achieve verification goals for IP, subsystem, and SoC from specification definition through to post-silicon verification closure.
• Provide final SoC DV signoff based on regression results, coverage metrics, and DV to specification traceability using C and/or SV-UVM, while adhering to ISO 26262/ISO 21434 guidelines.
• Actively participate in customer reviews and certification processes (ISO 26262/ISO 21434).

Skills

DV engineering

Verification strategy

Test benches

UVM

C/SystemVerilog

Cross-functional teamwork

Tools

SV-UVM

RTL/PARTL

GLS/PAGLS

C

SystemVerilog

Job description

Change the world. Love your job.

The MSP design team, part of Embedded Processing (EP), develops cutting-edge system-on-chips (SoCs) that are affordable and ultra-low-power, featuring integrated high-performance digital and analog peripherals for a wide range of applications in the industrial, automotive, and embedded sectors. The team is responsible for architecting and developing differentiated intellectual properties (IPs) and SoCs that minimize power consumption while delivering superior analog and computing performance. The team’s responsibilities include designing low-power SoC architectures, hardware accelerators, safety and security infrastructure, and application-specific control and communication peripherals. They also oversee the integration of these IPs into SoCs, along with implementation, tape-out, and post-silicon release-to-market enablement.

As a Verification Manager, you will play a crucial role in ensuring the quality and reliability of our advanced MSP products. Your duties will include verifying IPs, SoC designs, and assisting with customer debugging, while also contributing to the development of robust verification methodologies and strategies in accordance with ISO 26262/ISO 21434 standards.

Responsibilities:

End-to-End ownership of IP/subsystem/SOC DV/Post silicon debugs ownership right from spec definition till the post silicon verification and solving the customer issues. This includes:

Technical:

• Actively collaborate with the architecture team during the specification definition phase.
• Define the verification strategy along with a plan to ensure 100% traceability between specifications and regression, including standard signoff metrics.
• Conduct IP, SubSystem, and SoC verification, covering both functional and firmware scenarios in RTL/PARTL and GLS/PAGLS modes.
• IP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.
• Own the DV environment, which includes defining and developing test benches, enhancing UVC integration, updating checkers and coverage monitors, and adapting the DV flow as needed for the project.
• Proficient in analog and mixed-signal (AMS) verification, clock domain crossing (CDC) digital verification, formal verification, and post-silicon verification.
• Work closely with cross-functional teams - including Architecture, RTL, PD, DFT, Systems, Analog, Firmware, and Application teams - to achieve verification goals for IP, subsystem, and SoC from specification definition through to post-silicon verification closure.
• Provide final SoC DV signoff based on regression results, coverage metrics, and DV to specification traceability using C and/or SV-UVM, while adhering to ISO 26262/ISO 21434 guidelines.
• Actively participate in customer reviews and certification processes (ISO 26262/ISO 21434).