CXL IP Validation Lead

Capgemini Engineering; Bengaluru; On-site; INR 5,000,000 - 7,000,000; Full time

Job summary

Capgemini Engineering in Bengaluru seeks an experienced CXL IP Validation Engineer to own end-to-end post-silicon validation for CXL controller and subsystem IPs. You will architect test scenarios, drive coverage closure, and ensure smooth integration of CXL with high-speed interfaces.

You will lead validation plans, verify CXL and PCIe protocols, and develop directed and constrained-random tests, while mentoring junior engineers to achieve right-first-time delivery.

Qualifications

• 8–12 years of hands-on post-silicon IP/SoC validation experience.
• Deep knowledge of high-speed interfaces (PCIe, CXL, UCIe).
• Experience with PCI-SIG and CXL compliance workshops.

Responsibilities

• Test planning and architecture: define validation strategies and write test plans.
• Protocol verification: focus on CXL and PCIe protocols.
• Testing and coverage: create directed and constrained-random tests, run regressions, verify functionality and performance.
• Mentorship: lead and guide junior verification engineers for right-first-time delivery.
• Compliance and interoperability: ensure IP passes PCI-SIG and CXL Consortium workshops.

Skills

CXL IP verification

PCIe Gen5/6

Python scripting

Regression testing

Mentorship

Education

Bachelor's or Master’s in Electrical/Electronics/CS

Job description

Notice Period : Preferred Immediate joiners.

About the Role

We are seeking an experienced and highly technical CXL IP Validation Engineer to join our silicon IP validation team. In this role, you will own the end-to-end post-silicon validation of next-generation Compute Express Link (CXL) controller and subsystem IPs. You will architect test scenarios, drive coverage closure, and ensure seamless integration of CXL with other high-speed interfaces.

Key Responsibilities

• Test Planning & Architecture: Define validation strategies, author detailed test plans, and help execute them
• Protocol Verification: Focus heavily on verifying CXL protocols (CXL.io, CXL.cache, CXL.mem), as well as PCI Express (PCIe) Gen6/5.
• Testing & Coverage: Create directed and constrained-random tests, run regressions, and achieve functional and performance tests.
• Mentorship: Lead, guide, and mentor junior verification engineers to accelerate their growth and ensure right-first-time delivery.
• Compliance & Interoperability: Ensures the IP passes strict PCI-SIG and CXL Consortium compliance workshops using standard exercisers and analyzers (e.g., Teledyne LeCroy) to verify link layer training and state machines.

Basic Qualifications

• Education: Bachelor’s (B.E./B.Tech) or Master’s (M.S./M.Tech) degree in Electrical Engineering, Electronics, or Computer Science.
• Experience: 8 to 12 years of hands-on experience in post-silicon IP/SoC validation, with specific focus on high-speed interfaces.
• Deep understanding of micro-architecture for complex SOCs

Required Technical Skills

• Protocol Expertise: Deep understanding of PCIe, CXL, or UCIe protocols.
• Scripting: Good working knowledge of Python, Perl, or Tcl for automation.