Associate II - VLSI

UST

Bengaluru

On-site

INR 1,000,000 - 2,000,000

Full time

5 days ago

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Job summary

UST is seeking an ASIC Verification Engineer to join its verification team in Bengaluru. You will contribute to developing and executing verification plans for next-generation SoCs, building robust environments with UVM/SystemVerilog, and ensuring design quality using formal and emulation techniques.

The ideal candidate brings 2+ years of SoC/IP verification experience, strong programming skills in SystemVerilog, Verilog, Python, and C/C++, and the ability to collaborate with architecture and

Qualifications

Bachelor’s or Master’s in Electrical/Computer/Electronics or related field.
2+ years of experience in SoC/IP verification.
Strong understanding of digital design fundamentals and SoC architecture.
Hands-on experience with SoC-level functional and performance verification.
Strong proficiency in SystemVerilog and Verilog.
Experience with UVM and other methodologies (OVM/VMM).
Experience developing testbenches, test cases, and coverage models.
Proficiency in Python scripting and C/C++.
Experience with simulation tools: VCS, Xcelium.

Responsibilities

Develop and execute comprehensive ASIC verification plans and strategies.
Perform functional and performance verification of complex SoC designs using simulation, emulation, and formal verification techniques.
Create and maintain scalable verification environments using UVM and industry-standard methodologies.
Develop testbenches, test cases, scoreboards, assertions, and coverage models using SystemVerilog.
Execute core-level and SoC-level verification to ensure design correctness and performance targets are met.
Debug simulation failures, analyze verification results, and perform root-cause analysis of design issues.
Collaborate with architecture and RTL design teams to understand specifications and resolve functional issues.
Develop and enhance automation, scripting, and regression frameworks.
Document verification results, track project progress, and provide regular status updates.
Participate in design reviews, code reviews, and methodology improvement initiatives.

Skills

SystemVerilog/UVM

Python scripting

C/C++ programming

Verilog

Constrained Random Verification

Testbench development

Debugging/analysis

Automation scripting

Education

Bachelor’s or Master’s in Electrical/Computer/Electronics

Tools

Synopsys VCS

Cadence Xcelium

Job description

Who we are

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

Role Description

Who we are

Job Title

ASIC Verification Engineer

Summary

UST is looking for a Design Verification Engineer with expertise in UVM, SystemVerilog.

The Opportunity

We are seeking a highly motivated ASIC Design Verification Engineer to join our verification team and contribute to the development of next-generation products. The ideal candidate will be responsible for developing and executing comprehensive verification plans, building robust verification environments, and ensuring the quality and reliability of complex designs. This role offers the opportunity to work closely with architecture and design teams while leveraging industry-standard verification methodologies and tools.

Key Responsibilities

Develop and execute comprehensive ASIC verification plans and strategies

Perform functional and performance verification of complex SoC designs using simulation, emulation, and formal verification techniques

Create and maintain scalable verification environments using UVM and industry-standard methodologies

Develop testbenches, test cases, scoreboards, assertions, and coverage models using SystemVerilog.

Execute core-level and SoC-level verification to ensure design correctness and performance targets are met

Debug simulation failures, analyze verification results, and perform root-cause analysis of design issues

Collaborate with architecture and RTL design teams to understand specifications and resolve functional issues

Develop and enhance automation, scripting, and regression frameworks

Document verification results, track project progress, and provide regular status updates

Participate in design reviews, code reviews, and methodology improvement initiatives.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics, or a related field

2+ Years of experience in SoC/IP Verification

Strong understanding of digital design fundamentals and SoC architecture

Hands-on experience with SoC-level functional and performance verification

Strong proficiency in SystemVerilog and Verilog

Experience with UVM and other industry-standard verification methodologies (OVM/VMM)

Experience developing testbenches, testcases, and coverage models

Proficiency in Python scripting and C/C++ programming

Experience with simulation tools such as Synopsys VCS, Cadence Xcelium, or equivalent simulators

Strong debugging, analytical, and problem-solving skills

Excellent communication and teamwork skills

Preferred Qualifications

Experience with industry-standard protocols such as AXI, AHB, PCIe, DDR, and other SoC interconnects

Familiarity with formal verification methodologies and tools

Experience with assertion-based verification and coverage-driven verification techniques

Exposure to emulation-based verification environments

Knowledge of verification automation and regression infrastructure development

Understanding of processor-based SoCs and subsystem integration verification

Leadership Expectations

Take ownership of verification deliverables and quality metrics

Drive verification closure through effective coverage analysis and debug methodologies

Collaborate across design, architecture, and validation teams to deliver high-quality products

Contribute to reusable verification frameworks and methodology enhancements

Proactively identify verification risks and drive timely resolution

Demonstrate strong technical ownership and commitment to first-pass silicon success

What We Believe

We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone to champion diversity and inclusion and to place people at the centre of everything we do.

We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

Through business, we will better the lives of those less fortunate than ourselves.

We honour our commitments and act with responsibility in all our relationships.

Equal Employment Opportunity Statement

UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.

All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.

UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.