SOC Design Verification Engineer

UST; Ahmedabad District; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

UST is seeking a highly motivated SoC Verification Engineer to support the verification of complex System-on-Chip (SoC) designs. You will develop verification plans, build robust verification environments, and debug functional issues to ensure design quality, performance, and reliability.

The engineer will collaborate closely with design and architecture teams and contribute to the delivery of high-quality, production-ready silicon solutions.

Qualifications

• 8+ years of verification experience (IP/SOC).
• At least one full project in SoC verification.
• Experience with coverage-driven verification.
• Proven ability to verify complex digital designs.
• Familiarity with AMBA, PCIe, Ethernet, USB protocols is desired.
• Experience with formal verification is a plus.

Responsibilities

• Develop and implement comprehensive SoC verification plans.
• Build and maintain verification environments using UVM/OVM/VMM.
• Develop testbenches including stimulus, monitors, constraints, assertions, and scoreboards.
• Debug simulation failures and perform root-cause analysis.
• Collaborate with design and architecture teams to resolve issues.
• Enhance verification methodologies and processes.
• Document verification results and provide status updates.
• Participate in code and design reviews with constructive feedback.

Skills

SoC Architecture

Python

SystemVerilog

Formal Verification

Testbench Development

Digital Electronics

C

Cadence Xcelium

SystemC

Synopsys VCS

UVM

Education

Bachelor’s or Master’s degree in Electronics, Electrical, Computer Engineering, or related

Tools

Cadence Xcelium

Job description

Who We Are

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

Role Description

UST Title – Technical Lead I - VLSI

Who We Are

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

Summary

UST is looking for SOC Design Verification Engineer.

Job Description

We are seeking a highly motivated SoC Verification Engineer to support the verification of complex System-on-Chip (SoC) designs. The role involves developing and executing verification plans, building robust verification environments, and debugging functional issues to ensure design quality, performance, and reliability. The engineer will collaborate closely with design and architecture teams and contribute to the delivery of high-quality, production-ready silicon solutions.

Key Responsibilities

• Develop and execute comprehensive SoC verification plans


• Build and maintain verification environments using UVM/OVM/VMM


• Develop testbenches including stimulus, monitors, constraints, assertions, and scoreboards


• Debug simulation failures and perform root-cause analysis


• Collaborate with design and architecture teams on issue resolution


• Enhance verification methodologies and processes


• Document verification results and provide status updates


• Participate in code and design reviews, providing constructive feedback

Skills Required

• Strong understanding of digital design principles and SoC architecture


• Strong in Verilog and SystemVerilog


• Expertise in verification methodologies (UVM/OVM/VMM)


• Strong debugging and problem-solving skills


• Excellent communication and cross-team collaboration skills

Requirements

• Bachelor’s or master’s degree in Electronics, Electrical, Computer Engineering, or a related discipline


• 8+ years of Verification experience (IP/SOC), with at least one full project in SoC verification.


• Strong expertise in coverage-driven verification and industry-standard protocols (AMBA, PCIe, Ethernet, USB)


• Proven experience verifying complex digital designs


• Experience with formal verification is a plus

What We Believe

We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do.

Humility

We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

Humanity

Through business, we will better the lives of those less fortunate than ourselves.

Integrity

We honour our commitments and act with responsibility in all our relationships.

Equal Employment Opportunity Statement

UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.

All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.

UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.

• To support and promote the values of UST.


• Comply with all Company policies and procedures

Skills

SoC Architecture, Python, SystemVerilog, Formal Verification, Testbench Development, Digital Electronics, C, Cadence Xcelium, SystemC, Synopsys VCS, UVM