ASIC Physical Design Engineer

Ceremorphic, Inc.; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Ceremorphic, Inc. is seeking an experienced IC Physical Design Engineer in Hyderabad to own and drive the physical implementation of next-generation SOCs.

You will collaborate with architecture, front-end, and CAD teams to ensure high-quality physical designs and successful signoffs. The role requires hands-on expertise in floorplanning, clock tree synthesis, routing, and DRC/LVS, with strong TCL/Perl scripting skills and Cadence flows.

Qualifications

• Hands-on expertise in floorplanning, power planning, and physical design flows.
• Experience with timing closure and physical verification (DRC/LVS).
• Knowledge of EM/IR, Crosstalk, and double patterning is beneficial.

Responsibilities

• Define physical implementation methodologies and drive SOC realization.
• Collaborate with architecture, design, front end, and CAD teams to deliver physical designs.
• Implement and verify designs at all levels of SOC hierarchy.
• Interact with foundry on technology, schedule, and signoff.
• Supervise resource allocation and scheduling.

Skills

Floorplanning

Power planning

Logic and clock tree synthesis

Placement

Timing Closure

Routing

Extraction

Physical Verification (DRC LVS)

Crosstalk Analysis

EM/IR

TCL/Perl programming

Cadence RTL-to-GDSII flow

Tools

Cadence RTL-to-GDSII flow

TCL programming

Perl programming

Job description

Ceremorphic AI hardware combines knowledge across many domains, including AI, compilers, computer architecture, analog circuits, and memories.

The candidate would own and drive the physical implementation of next-generation SOCs and assume the below responsibilities.

• Understand the requirements and define physical implementation methodologies.
• Collaborate with architecture, design, front end, and CAD teams to deliver high-quality physical designs.
• Implement and verify designs at all levels of hierarchy in the SOC.
• Interact with foundry over matters of technology, schedule, and signoff
• Supervise resource allocation and scheduling.

Key Requirements

• Hands-on expertise in all of the following areas: Floorplanning, Power planning, Logic and clock tree synthesis, Placement, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
• Full chip/ top-level expertise in multiple chip tape-outs.
• Good understanding of SCAN, BIST, and ATPG.
• Strong background in TCL/Perl programming is a must.
• Expertise in double patterning process nodes is desirable.
• Expertise in Cadence RTL-to-GDSII flow is preferred.