Title: ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 yea[...]

Cisco Systems, Inc.; Pune District; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Cisco Systems, Inc. in Pune District seeks a Verification Engineer to work with a team on cutting-edge optical transceivers. You will develop verification documentation, conduct block and chip level verification, and debug complex verification issues.

Ideal candidates should have 12-16 years of experience, strong skills in SystemVerilog, Python, C, and UVM methodology, alongside excellent organizational and communication abilities.

Qualifications

• 12-16 years of functional verification experience.
• Strong skills in SystemVerilog, Python, C, and UVM methodology.
• Good understanding of CPU sub-systems, FPGA, and protocols.

Responsibilities

• Develop testbench components for Silicon Photonics subsystems.
• Conduct block and full chip verification.
• Debug complex verification issues within a UVM-based framework.

Skills

SystemVerilog

Python

C

UVM methodology

Analytical skills

Debugging skills

Teamwork

Communication skills

Education

Bachelor’s or Masters in Electronics Engineering

Tools

Simulation tools (Synopsys, Cadence, Mentor Graphics)

Job description

Meet the Team

Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.

You will work with Cisco's outstanding Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.

Your Impact

As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept phase you will create verification documentation and work with senior engineers to help with defining the verification methodology and developing testbench components. During the initial design phase, you will be a part of block level verification and then you will transition to full chip verification. You will run verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions. You will develop functional coverage models, assertions, and debug complex verification issues within a UVM-based framework. Prior to tapeout you will run functional scenarios with CPU FW loaded and verify functionality at the CPU sub-system level. You may be involved in FPGA verification. Post Silicon you will be involved in ATE test plan and test vector generation, ATE testing and release to production.

• Develop testbench components for Silicon Photonics subsystems. Proven ability to build UVM components (agents, drivers, monitors, scoreboards, sequences) and implement constrained-random and directed test strategies
• Ability to understand coverage metrics and functional specifications
• Understand and implement verification scenarios per full chip analog and digital verification test plans
• Analyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs
• FW/C-Coding and verification of CPU sub-systems with FW
• Must have good knowledge of Python and C. Develop scripts for automated analysis and reports
• Good understanding of RTL digital design and DFT (Design for Test) principles
• Excellent organizational, teamwork, and communication skills

Minimum Qualifications

• Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
• 12-16 years of functional verification experience
• Strong skills in SystemVerilog, Python, C and UVM methodology
• Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
• Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols
• Experience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow
• You must be a team player and be able to drive decisions quickly with consensus building.
• Strong analytical, problem-solving and debugging skills
• Strong teamwork, communication, and organizational skills