ASIC Engineer, Implementation

Meta Careers; Bengaluru; On-site; INR 3,000,000 - 4,500,000; Full time

Job summary

Meta is building custom silicon to power AI, AR and VR at scale. An ASIC Implementation Engineer will contribute to the physical implementation of complex ASICs from RTL through tape-out, collaborating across synthesis, place-and-route, timing closure and sign-off.

The role requires working with design, architecture, and verification teams to deliver high-performance, power-efficient silicon for Meta's data center and compute infrastructure.

Qualifications

• Experience in RTL to GDSII flow for SoCs.
• Strong debugging and problem-solving skills across timing, power and area.
• Ability to work with design/verification teams to meet tight schedules.

Responsibilities

• Run logic/physical synthesis and generate optimized gate-level netlists.
• Debug timing, area, and congestion with RTL/physical designers.
• Perform RTL/ gate-level power estimation and identify reduction opportunities.
• Run formal verification between RTL and gate-level netlists and debug failures.
• Perform RTL lint and create waivers with designers.
• Perform RTL DFT analysis to improve coverage.
• Develop timing constraints for RTL synthesis and PrimeTime-STA for blocks/top-level.
• Analyze inter-block timing and IO budgets for partitions.
• Develop automation scripts for Lint, CDC, RDC, Synthesis, STA, Power.

Skills

RTL knowledge

Timing analysis

Power optimization

DFT analysis

Automation scripting

Debugging

Tools

PrimeTime-STA

Lint tools

Synthesis tools

Power analysis

Formal verification

Job description

# ASIC Engineer, ImplementationBangalore, India Hardware+ 2 moreApply nowMeta is building custom silicon to power the next generation of infrastructure supporting AI, augmented reality, and virtual reality at scale. As an ASIC Implementation Engineer on the Infrastructure Silicon team, you will contribute to the physical implementation of complex custom ASICs from RTL through tape-out, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will collaborate with design, architecture, and verification teams to deliver high-performance, power-efficient silicon that meets the demanding requirements of Meta's data center and compute infrastructure.---## ASIC Engineer, Implementation Responsibilities* Run Logic/Physical Synthesis using advanced optimization techniques and generate an optimized Gate Level Netlist for Timing, Area, and Power* Debug the timing/area/congestion issues and work with RTL and physical designers to resolve them* Perform power estimation at RTL and gate level, and identify power reduction opportunities* Run Formal Verification checks between RTL and gate-level netlist, and debug the aborts, inconclusive, and logic equivalency failures* Perform RTL Lint and work with the designers to create waivers* Perform RTL DFT analysis and improve the DFT coverage for stuck-at faults* Develop timing constraints for RTL synthesis and PrimeTime-STA for the blocks and the top-level including SoC* Analyze the inter-block timing and come up with I/O budgets for the various partition blocks* Developing automation scripts and methodology for all FE tools including (Lint, CDC, RDC, Synthesis, STA, Power)