ASIC Engineer Intern, Design

Meta Careers; Bengaluru; On-site; INR 201,000 - 268,000; Full time

Job summary

Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization in Bengaluru. You will contribute to design and verification of advanced IPs and help build accelerators for data center workloads.

During the 12 to 16 week internship, you will participate in micro-architecture reviews, develop RTL or HLS code, analyze PPA, and support verification infrastructure to improve coverage. Join a team that values hands-on learning and scalable infrastructure.

Qualifications

• Bachelor's degree candidate in Electrical or Computer Engineering or related field.
• Knowledge of Verilog/SystemVerilog or HLS.
• Understanding of computer architecture and logic design fundamentals.

Responsibilities

• Participate in micro-architecture, design, and verification reviews and provide feedback.
• Design and develop RTL or HLS code for IPs.
• Analyze designs and optimize power, performance, and area (PPA).
• Support verification infrastructure and improve verification coverage.

Skills

Verilog

SystemVerilog

HLS

Computer Architecture

Logic Design

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Job description

# ASIC Engineer Intern, DesignBangalore, India Hardware+ 2 moreApply nowMeta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design and verification of advanced IPs using state of the art tools. Come work and learn alongside our engineers to build “Green” data center accelerators.Internships are twelve (12) to sixteen (16) weeks long.---## ASIC Engineer Intern, Design Responsibilities* Participate in Micro-architecture, Design, and Verification reviews and provide feedback* Design and develop RTL or HLS code for some of the IPs* Analyze designs and enhance PPA (Power, Performance, Area)* Support and develop Verification Infrastructure, analyze and improve Verification Coverage* Support Simulation accelerators and post-Silicon validation## Minimum Qualifications* Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields* Knowledge of Verilog or System Verilog or HLS* Knowledge of Computer Architecture and Logic Design fundamentals