ASIC Design Engineer

Hewlett Packard Enterprise; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Benefits offered by this job

Comprehensive health & wellbeing benefits

Personal & professional development programs

Diversity and inclusion initiatives

Job summary

Hewlett Packard Enterprise is looking for a skilled ASIC Designer to define and architect high-performance networking blocks. The ideal candidate will collaborate with verification and physical design teams while demonstrating exceptional Verilog skills and a strong understanding of networking protocols.

This role is onsite in Bengaluru, India, offering comprehensive health benefits, professional development opportunities, and a commitment to diversity and inclusion.

Qualifications

• 5+ years of experience in ASIC design for networking protocols.
• Knowledge of high performance memory subsystems required.
• Experience with Agile methodologies preferred.

Responsibilities

• Define and architect high-performance blocks for networking ASICs.
• Collaborate with teams for developing and debugging test plans.
• Analyze timing violations and perform timing fixes.

Skills

Strong Verilog RTL coding skills

Knowledge of Synopsys Design Compiler

Knowledge of multi-domain clock synchronization

Strong problem solving skills

Excellent written and verbal communication skills

Education

MSEE or BSEE

Job description

Role Overview

This role has been designed as Onsite with an expectation that you will primarily work from an HPE office.

What You’ll Do

• Define and architect high-performance blocks for the latest, most advanced networking ASICs
• Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
• Collaborate with the verification team in the development of the testplan and assist in debugging test failures
• Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

What You Need To Bring

• Strong Verilog RTL coding skills
• Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
• Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
• Knowledge of high performance memory subsystems
• Knowledge of multi-domain clock synchronization and high-speed serial interfaces
• Strong problem solving and ASIC debugging skills
• Excellent written and verbal communications skills
• MSEE or BSEE is required with 5 plus years of experience

Additional Skills

• Accountability
• Accountability
• Action Planning
• Active Learning
• Active Listening
• Agile Methodology
• Agile Scrum Development
• Analytical Thinking
• Bias
• Coaching
• Creativity
• Critical Thinking
• Cross-Functional Teamwork
• Data Analysis Management
• Data Collection Management (Inactive)
• Data Controls
• Design
• Design Thinking
• Empathy
• Follow-Through
• Group Problem Solving
• Growth Mindset
• Intellectual Curiosity (Inactive)
• Long Term Planning
• Managing Ambiguity {+ 5 more}

Benefits

• Comprehensive health & wellbeing benefits that support physical, financial and emotional wellbeing
• Personal & professional development programs
• Diversity and inclusion initiatives that celebrate individual uniqueness

Equal Employment Opportunity

HPE is an Equal Employment Opportunity/Veteran/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.