STA Design Engineer (Visas Supported)

European Tech Recruit; Cork; On-site; EUR 70,000 - 110,000; Full time

Job summary

European Tech Recruit seeks an experienced STA Engineer to join the R&D Centre in Cork, Ireland. You will perform static timing analysis, develop timing constraints, and optimize timing performance for high‑performance, low‑power SoCs and cores.

You will collaborate with cross-functional teams to ensure timing closure, validate timing models, and drive automation for timing and power data mining while supporting production and project milestones.

Qualifications

• 4+ years of related work experience.
• Proficient in STA tools for hierarchical analysis in large SoCs.
• Hands-on with timing closure tools.
• Strong automation skills in Python, TCL or Perl.
• Good knowledge of ASIC design flows (RTL-to-GDS).

Responsibilities

• Perform static timing analysis and timing closure for cores and SOCs.
• Develop timing constraints and optimize timing performance.
• Collaborate with cross-functional teams to ensure timing closure.
• Automate timing and power data mining and processing.
• Contribute to project milestones and delivery.
• Provide production support and resolve issues during development.

Skills

STA expertise

Automation scripting

ASIC design flows

Problem-solving

Communication

Tools

PrimeTime

PrimeShield

Tempus

Tweaker

PrimeClosure

PTECO

Tempus ECO

Job description

STA Engineer

An exciting career opportunity for an experienced STA Engineer to join a Global Leading Semiconductor company, where you will will perform static timing analysis, develop timing constraints, and optimize timing performance for a variety of high-performance, high-quality, low-power world-class products.

The STA team at is responsible for evaluating block-level and top-level timing to ensure optimal performance and power efficiency in advanced cores and SOCs. You will collaborate with cross-functional teams to ensure timing closure and validate timing models, contributing to the successful execution of product development at the companies R&D Centre in Cork, Ireland.

Responsibilities:

• You will be a member of a team working on timing signoff for Snapdragon Cores and SOCs, methodologies and flows: Performing STA and timing closure for complex cores and full-chip SOCs
• Enhancing techniques and methodologies for STA and timing closure
• Driving accuracy of timing closure and static/dynamic flows to reduce turnaround time
• Ensuring compliance with timing signoff checklists and criteria
• Automation for timing and power data mining and processing
• Participating in project proposal development including key milestones and deliverables
• Executing and delivering project goals in a timely manner with production support
• Resolving issues in all phases of development to ensure smooth project execution

About You:

• 4+ years of related work experience
• Expertise in STA tools (PrimeTime, PrimeShield or Tempus) used for hierarchical analysis in large SoCs
• Hands-on experience with Tweaker, PrimeClosure, PTECO, or Tempus ECO for timing closure
• Highly proficient in automation: Python, TCL or Perl
• Strong knowledge of ASIC design flows (RTL-to-GDS)
• Interest in Design for Parametric Yield is an added advantage
• Comfortable with extraction, circuit simulation tools and environments is a plus
• Excellent problem-solving skills and result-driven approach, able to work and drive practical solutions under research environment.
• Good communication and personal skills in a multi-disciplinary, fast-paced engineering environment

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