Static Timing Analysis Design Engineer

European Tech Recruit; Cork; On-site; EUR 70,000 - 100,000; Full time

Job summary

European Tech Recruit is partnering with a multinational semiconductor company in Cork to hire an experienced Static Timing Analysis Design Engineer. The role focuses on STA, timing constraints, and optimization for high-performance SOCs.

You will collaborate with cross-functional teams to ensure timing closure, validate models, and contribute to successful product development in a fast-paced engineering environment.

Qualifications

• Expertise in STA tools (PrimeTime, PrimeShield or Tempus) used for hierarchical analysis in large SoCs.
• Hands-on experience with Tweaker, PrimeClosure, PTECO, or Tempus ECO for timing closure.
• Highly proficient in automation: Python, TCL or Perl.

Responsibilities

• Perform STA and timing closure for complex cores and full-chip SOCs.
• Enhance techniques and methodologies for STA and timing closure.
• Drive accuracy of timing closure and static/dynamic flows to reduce turnaround time.
• Ensure compliance with timing signoff checklists and criteria.
• Automate timing and power data mining and processing.
• Participate in project proposal development including milestones and deliverables.
• Execute and deliver project goals with production support.
• Resolve issues in all phases of development to ensure smooth project execution.

Skills

Python

TCL

Perl

RTL-to-GDS

ASIC design flows

problem-solving

communication

Tools

PrimeTime

PrimeShield

Tempus

Tweaker

PrimeClosure

PTECO

Tempus ECO

Job description

European Tech Recruit are working closely with a multinational semiconductor technology company, based in Cork, who are looking for an experienced Static Timing Analysis Design Engineer to join their team.

As an STA Engineer, you will perform static timing analysis, develop timing constraints, and optimize timing performance for a variety of high-performance, high-quality, low-power world-class products. You will collaborate with cross-functional teams to ensure timing closure and validate timing models, contributing to the successful execution of product development.

Responsibilities as Static Timing Analysis Design Engineer:

• Performing STA and timing closure for complex cores and full-chip SOCs.
• Enhancing techniques and methodologies for STA and timing closure.
• Driving accuracy of timing closure and static/dynamic flows to reduce turnaround time.
• Ensuring compliance with timing signoff checklists and criteria.
• Automation for timing and power data mining and processing.
• Participating in project proposal development including key milestones and deliverables.
• Executing and delivering project goals in a timely manner with production support.
• Resolving issues in all phases of development to ensure smooth project execution.

Requirements:

• Expertise in STA tools (PrimeTime, PrimeShield or Tempus) used for hierarchical analysis in large SoCs.
• Hands-on experience with Tweaker, PrimeClosure, PTECO, or Tempus ECO for timing closure.
• Highly proficient in automation: Python, TCL or Perl.
• Strong knowledge of ASIC design flows (RTL-to-GDS).
• Interest in Design for Parametric Yield is an added advantage.
• Comfortable with extraction, circuit simulation tools and environments is a plus.
• Excellent problem-solving skills and result-driven approach, able to work and drive practical solutions under research environment.
• Good communication and personal skills in a multi-disciplinary, fast-paced engineering environment.

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