Staff Front-End Implementation Engineer, ASIC/SoC

Qualcomm; Cork; On-site; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Salary and bonuses

Maternity/Paternity Leave

Employee stock purchase scheme

Matching pension scheme

Education Assistance

Relocation assistance

Life/Medical/Travel Insurance

Well-being subsidies

Job summary

QT Technologies Ireland Limited in Cork, Ireland, invites an experienced Front-End Implementation Engineer to shape the timing-closure and physical-synthesis flow for Snapdragon SoCs at 4nm and below. You will bridge RTL and physical design, delivering ECOs, formal verification and low-power checks within the Cork team.

Ideal candidates hold a Master/PhD in Electronics or Computer Engineering with 5–10 years in ASIC design, timing constraints and TCL/Script development for CAD flows.

Qualifications

• Bachelor's degree in Science/Engineering with 4+ years ASIC experience.
• Masters in Science/Engineering with 3+ years ASIC experience.
• PhD with 2+ years ASIC experience.

Responsibilities

• Bridge RTL and physical design through timing constraints and ECOs.
• Work on top-level timing constraints, physical synthesis and formal verification.
• Contribute to low-power checks and DFT implementations.

Skills

Logical/Physical synthesis

DFT implementation

Timing closure in STA

Verilog RTL design

UPF, Low power checks

TCL scripting

Python/Perl scripting

Education

Bachelor's degree in Electronics or Computer Engineering

Master's degree in Electronics or Computer Engineering

PhD in Science/Engineering (related field)

Tools

TCL scripts development

PERL/Python scripting

Cadence/Synopsys flow knowledge

Formal verification tools

Job description

QT Technologies Ireland Limited in Cork, Ireland, invites an experienced Front-End Implementation Engineer to shape the timing-closure and physical-synthesis flow for Snapdragon SoCs at 4nm and below. You will bridge RTL and physical design, delivering ECOs, formal verification and low-power checks within the Cork team.

Ideal candidates hold a Master/PhD in Electronics or Computer Engineering with 5–10 years in ASIC design, timing constraints and TCL/Script development for CAD flows.