Sensor ASIC Verification Engineer – UVM & SystemVerilog

European Tech Recruit; Cork; On-site; EUR 70,000 - 110,000; Full time

Job summary

European Tech Recruit partners with a leading semiconductor company in Ireland to hire a Sensors Design Verification Engineer. The role focuses on UVM, formal verification, constrained-random testing, SystemVerilog assertions, C-model integration, and coverage closure for sensor algorithms.

Join a hands-on verification team and help deliver sensor RTL to ASIC tape-out, working with design and systems engineers to define objectives and improve regression infrastructure for scalable verification.

Qualifications

• Bachelor's degree in Science, Engineering, or a related technical discipline.
• 4+ years of ASIC design verification, UVM-based functional verification, or related experience.
• Strong hands-on experience with UVM and SystemVerilog.
• Strong understanding of coverage-driven verification methodologies.
• Proven experience developing and maintaining UVM verification environments and flows.
• Strong experience writing and implementing SystemVerilog Assertions.
• Experience analysing verification coverage and driving code, functional, and line coverage towards closure.
• Strong debugging skills, particularly around test failures and RTL simulation results.

Responsibilities

• Deploy industry-leading verification methodologies including UVM and Formal Verification.
• Develop scalable and reusable verification environments, including UVCs, C models, and vertical/horizontal verification components.
• Verify sensor algorithm RTL to ASIC tape-out quality.
• Develop detailed test plans based on design specifications and requirements.
• Work closely with design and systems engineers to define verification objectives and coverage targets.
• Integrate C models within UVM-based verification environments.
• Develop and maintain SystemVerilog Assertions (SVA) for functional and protocol verification.
• Debug, verify, and optimise RTL behaviour while ensuring bit-exact matching against reference test vectors.
• Analyse coverage data and work with design teams to identify and close coverage gaps.
• Develop and enhance regression frameworks to improve verification efficiency and scalability.

Skills

UVM

SystemVerilog

Formal verification

Coverage-driven verification

SystemVerilog Assertions (SVA)

C-model integration

Regression frameworks

RTL debugging

Education

Bachelor's degree in Science/Engineering

Tools

UVCs

Jasper

VC Formal

Job description

European Tech Recruit partners with a leading semiconductor company in Ireland to hire a Sensors Design Verification Engineer. The role focuses on UVM, formal verification, constrained-random testing, SystemVerilog assertions, C-model integration, and coverage closure for sensor algorithms.

Join a hands-on verification team and help deliver sensor RTL to ASIC tape-out, working with design and systems engineers to define objectives and improve regression infrastructure for scalable verification.