Design Verification Engineer - ASIC / UVM / SystemVerilog / Sensor Algorithms

European Tech Recruit; Cork; On-site; EUR 70,000 - 110,000; Full time

Job summary

European Tech Recruit partners with a leading semiconductor company in Ireland to hire a Sensors Design Verification Engineer. The role focuses on UVM, formal verification, constrained-random testing, SystemVerilog assertions, C-model integration, and coverage closure for sensor algorithms.

Join a hands-on verification team and help deliver sensor RTL to ASIC tape-out, working with design and systems engineers to define objectives and improve regression infrastructure for scalable verification.

Qualifications

• Bachelor's degree in Science, Engineering, or a related technical discipline.
• 4+ years of ASIC design verification, UVM-based functional verification, or related experience.
• Strong hands-on experience with UVM and SystemVerilog.
• Strong understanding of coverage-driven verification methodologies.
• Proven experience developing and maintaining UVM verification environments and flows.
• Strong experience writing and implementing SystemVerilog Assertions.
• Experience analysing verification coverage and driving code, functional, and line coverage towards closure.
• Strong debugging skills, particularly around test failures and RTL simulation results.

Responsibilities

• Deploy industry-leading verification methodologies including UVM and Formal Verification.
• Develop scalable and reusable verification environments, including UVCs, C models, and vertical/horizontal verification components.
• Verify sensor algorithm RTL to ASIC tape-out quality.
• Develop detailed test plans based on design specifications and requirements.
• Work closely with design and systems engineers to define verification objectives and coverage targets.
• Integrate C models within UVM-based verification environments.
• Develop and maintain SystemVerilog Assertions (SVA) for functional and protocol verification.
• Debug, verify, and optimise RTL behaviour while ensuring bit-exact matching against reference test vectors.
• Analyse coverage data and work with design teams to identify and close coverage gaps.
• Develop and enhance regression frameworks to improve verification efficiency and scalability.

Skills

UVM

SystemVerilog

Formal verification

Coverage-driven verification

SystemVerilog Assertions (SVA)

C-model integration

Regression frameworks

RTL debugging

Education

Bachelor's degree in Science/Engineering

Tools

UVCs

Jasper

VC Formal

Job description

Design Verification Engineer - ASIC / UVM / SystemVerilog / Sensor Algorithms

We are currently partnered with a leading semiconductor technology company developing advanced sensor technologies and high-performance ASIC solutions. As part of their continued engineering growth, they are looking to hire a Sensors Design Verification Engineer to support the verification of sensor algorithm RTL through to ASIC tape-out.

This is a hands-on verification role focused on UVM, formal verification, constrained-random testing, SystemVerilog assertions, C-model integration, coverage closure, regression infrastructure, and sensor algorithm verification.

Key Responsibilities

• Deploy industry-leading verification methodologies including UVM and Formal Verification


• Develop scalable and reusable verification environments, including UVCs, C models, and vertical/horizontal verification components


• Verify sensor algorithm RTL to ASIC tape-out quality


• Develop detailed test plans based on design specifications and requirements


• Work closely with design and systems engineers to define verification objectives and coverage targets


• Integrate C models within UVM-based verification environments


• Develop and maintain SystemVerilog Assertions (SVA) for functional and protocol verification


• Debug, verify, and optimise RTL behaviour while ensuring bit-exact matching against reference test vectors


• Analyse coverage data and work with design teams to identify and close coverage gaps


• Develop and enhance regression frameworks to improve verification efficiency and scalability

Key Requirements

• Bachelor's degree in Science, Engineering, or a related technical discipline


• 4+ years of ASIC design verification, UVM-based functional verification, or related experience


• Strong hands-on experience with UVM and SystemVerilog


• Strong understanding of coverage-driven verification methodologies


• Proven experience developing and maintaining UVM verification environments and flows


• Strong experience writing and implementing SystemVerilog Assertions


• Experience analysing verification coverage and driving code, functional, and line coverage towards closure


• Strong debugging skills, particularly around test failures and RTL simulation results

Keywords

Sensors Design Verification Engineer / ASIC Verification / Digital Verification / Sensor Verification / Sensor ASIC / SoC Verification / IC Verification / UVM / SystemVerilog / Verilog / RTL Verification / Functional Verification / Formal Verification / Jasper / VC Formal / SystemVerilog Assertions / SVA / Constrained Random Verification / Coverage Driven Verification / Coverage Closure / Code Coverage / Functional Coverage / Line Coverage / C Model / C++ / SystemC / MATLAB / Python / Perl / Shell Scripting / UVC / Verification Components / UVM Testbench / Testbench Development / Verification Environment / Regression Testing / Regression Framework / RTL Simulation / Gate Level Simulation / Test Vector Debug / Bit Exact Verification / ASIC Tapeout / ASIC Design / Sensor Algorithms / Digital Design / Hardware Verification / Verification Automation / Verification Methodology / Subsystem Integration / Hardware Debug / Semiconductor / Integrated Circuits / Digital IC / SoC / Technical Reviews / Verification Planning / Design Verification / ASIC Engineering

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