Senior Design Verification Engineer: RTL/UVM Expert

European Tech Recruit; Munster; On-site; EUR 90,000 - 120,000; Full time

Job summary

European Tech Recruit are working with a leading semiconductor company in Cork seeking a Senior Design Verification Engineer to join their team.

You will develop and maintain testbenches, verify RTL, create test plans, and improve verification environments using UVM, SystemVerilog, Python and C models. The role emphasizes gate-level debugging, coverage-driven verification, and collaboration with design and systems engineers.

Qualifications

• 3+ years in ASIC design verification or UVM-based verification.
• Experience with gate-level simulation debugging and power extraction tools is an advantage.
• Strong UVM/SystemVerilog knowledge and shell scripting (Perl/Python).

Responsibilities

• Develop and maintain testbenches and verification components.
• Verify RTL of sensor algorithms to meet ASIC tapeout standards.
• Create comprehensive test plans based on design specifications.
• Integrate C models into the UVM framework.
• Document verification activities, results, and methodologies.

Skills

UVM-based verification

SystemVerilog

RTL simulation

Python

C/C++

Formal verification

Debugging

Testbench development

Education

Bachelor’s degree in Science, Engineering, or related field

Tools

RTL simulation tools

Power extraction tools

C/C++

SystemC

Job description

European Tech Recruit are working with a leading semiconductor company in Cork seeking a Senior Design Verification Engineer to join their team.

You will develop and maintain testbenches, verify RTL, create test plans, and improve verification environments using UVM, SystemVerilog, Python and C models. The role emphasizes gate-level debugging, coverage-driven verification, and collaboration with design and systems engineers.