Senior MCU Sub-System Verification Engineer

Qualcomm; Cork; On-site; EUR 65,000 - 95,000; Full time

Benefits offered by this job

Salary and performance bonus

Employee stock purchase scheme

Maternity/Paternity Leave

Matching pension scheme

Education Assistance

Relocation and immigration support

Life, Medical, Income and Travel Insur

Subsidised well-being memberships

Bike scheme

Employee clubs

Job summary

Qualcomm Cork is seeking an ASIC/SoC design verification engineer to develop verification plans for microcontroller and subsystem IPs. You will build and maintain UVM environments, implement constrained-random and coverage-driven verification, and drive coverage closure through rigorous debugging and analysis.

The role requires collaboration with design, architecture, and validation teams to resolve issues and improve verification flows.

Qualifications

• Bachelor’s degree required or equivalent in a relevant engineering discipline.
• Experience with ASIC/SoC verification.
• Proficiency with SystemVerilog/UVM and verification methodologies.

Responsibilities

• Develop and execute verification plans for microcontroller and subsystem IPs.
• Create and maintain UVM-based verification environments, testbenches, and reusable verification components.
• Develop constrained-random and coverage-driven verification solutions.
• Perform coverage analysis and drive closure.
• Collaborate with design, architecture, SoC integration, and validation teams to identify and resolve issues.
• Debug simulation failures and root-cause complex problems.
• Support test planning and debug for subsystem and SoC integration.

Skills

SystemVerilog

UVM

Constrained-random

Coverage-driven verification

Python

RTL simulation

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

JasperGold

Job description

Qualcomm Cork is seeking an ASIC/SoC design verification engineer to develop verification plans for microcontroller and subsystem IPs. You will build and maintain UVM environments, implement constrained-random and coverage-driven verification, and drive coverage closure through rigorous debugging and analysis.

The role requires collaboration with design, architecture, and validation teams to resolve issues and improve verification flows.