Senior Design Verification Engineer

European Tech Recruit; Munster; On-site; EUR 90,000 - 120,000; Full time

Job summary

European Tech Recruit are working with a leading semiconductor company in Cork seeking a Senior Design Verification Engineer to join their team.

You will develop and maintain testbenches, verify RTL, create test plans, and improve verification environments using UVM, SystemVerilog, Python and C models. The role emphasizes gate-level debugging, coverage-driven verification, and collaboration with design and systems engineers.

Qualifications

• 3+ years in ASIC design verification or UVM-based verification.
• Experience with gate-level simulation debugging and power extraction tools is an advantage.
• Strong UVM/SystemVerilog knowledge and shell scripting (Perl/Python).

Responsibilities

• Develop and maintain testbenches and verification components.
• Verify RTL of sensor algorithms to meet ASIC tapeout standards.
• Create comprehensive test plans based on design specifications.
• Integrate C models into the UVM framework.
• Document verification activities, results, and methodologies.

Skills

UVM-based verification

SystemVerilog

RTL simulation

Python

C/C++

Formal verification

Debugging

Testbench development

Education

Bachelor’s degree in Science, Engineering, or related field

Tools

RTL simulation tools

Power extraction tools

C/C++

SystemC

Job description

European Tech Recruit are working closely with a leading semicon company, based in the county Cork area, who are looking for a talented Senior Design Verification Engineer to join their team.

Responsibilities as Senior Design Verification Engineer:

• Apply leading-edge verification methodologies, including UVM and Formal Verification, to ensure high-quality deliverables.
• Develop and maintain testbenches and verification components such as UVCs, C models, and reusable vertical and horizontal verification environments.
• Verify RTL of sensor algorithms to meet ASIC tapeout quality standards.
• Create comprehensive test plans based on design specifications and collaborate with design and systems engineers for validation.
• Integrate C models into the UVM framework for efficient verification.
• Write and maintain SystemVerilog assertions to enforce design correctness.
• Perform debugging, verification, optimization, and bit-exact comparisons with provided test vectors.
• Support the integration of designs into higher-level subsystems, including test planning, test vector generation, and debugging at the integration stage.
• Utilize Python automation to streamline workflows and improve team productivity.
• Document all verification activities, including test plans, results, and methodologies.

Requirements:

• Bachelor’s degree in Science, Engineering, or a related field.
• Minimum 3 years of experience in ASIC design verification, UVM-based functional verification, or a related role.
• Experience with gate-level simulation debugging and power extraction tools is an advantage.
• Strong experience building and managing constrained-random verification environments using UVM and coverage-driven verification methodologies.
• Extensive experience using RTL simulation tools.
• Proficiency in UVM, SystemVerilog, and shell scripting (Perl/Python).
• Familiarity with C/C++ is a plus.
• Debugging experience.
• Experience with formal verification tools a bonus.
• Familiarity with SystemC and Matlab is a bonus.

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