Senior Verification Architect – Test Strategy & Innovation

Infineon Technologies AG; Dublin; On-site; EUR 90,000 - 120,000; Full time

Job summary

Infineon Technologies AG is seeking a Senior Staff Engineer Verification in our Research & Development team in Ireland. You will shape verification infrastructure, define strategies for IP/Subsystem and SOC verification, and work across UVM/OVM/SV methodologies to ensure robust designs.

Responsibilities include developing scalable test benches, documenting test plans, and collaborating with design and post-Silicon teams for validation testing.

Qualifications

• Master's degree in Electrical Engineering with 5–7 years of work experience, or a Bachelor's degree with 7–9 years.
• Solid understanding of verification methodologies, metrics, and flows (UVM/OVM/SystemVerilog).
• Knowledge of protocols like AHB, AMBA, AXI, SPI, LIN, UART is highly desirable.
• Knowledge of Automotive Functional safety concepts; ISO 26262 qualification is a plus.
• Strong initiative, analytical/problem-solving, teamwork, and multitasking.
• Fluency in English with excellent written and verbal communication.

Responsibilities

• Define verification infrastructure and scalable test bench components across projects.
• Define verification strategy for IP/Subsystem and SOC verification.
• Work with various verification methodologies (UVM/OVM/SV).
• Develop and debug random constraint verification test suites to verify DUT.
• Collaborate with design and post-Silicon teams for validation testing.

Skills

Verification methodologies

UVM

OVM

SystemVerilog

Test bench design

Problem solving

Teamwork

English fluency

Education

Master's degree in Electrical Engineering

Bachelor's degree in Electrical Engineering

Tools

Simulation tools (SV/Verilog)

Formal verification tools

Job description

Infineon Technologies AG is seeking a Senior Staff Engineer Verification in our Research & Development team in Ireland. You will shape verification infrastructure, define strategies for IP/Subsystem and SOC verification, and work across UVM/OVM/SV methodologies to ensure robust designs.

Responsibilities include developing scalable test benches, documenting test plans, and collaborating with design and post-Silicon teams for validation testing.