Senior Timing Engineer - ASIC Library Characterization

European Tech Recruit; Cork; On-site; EUR 90,000 - 130,000; Full time

Job summary

European Tech Recruit is seeking a Senior Timing Engineer for ASIC timing analysis, library characterization, and timing signoff across STA, LVF, AOCV/POCV/SOCV. You will work across library models, signoff tools, and SPICE simulations, coordinating with P&R and STA teams.

The role requires a Master’s degree and 3+ years of ASIC experience, with hands-on flows for library characterization and timing modelling.

Qualifications

• Master's degree in Electrical/Electronic Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• 3+ years of experience in ASIC design, timing, verification, validation, or related semiconductor engineering.
• Strong experience in ASIC timing analysis and timing signoff.
• Deep understanding of standard-cell library characterization and timing modelling processes.
• Hands-on experience with library characterization flows and methodologies.

Responsibilities

• Own and contribute to timing-related activities across advanced ASIC, IP, and SoC development programmes.
• Develop, maintain, and improve standard-cell library characterization methodologies and flows.
• Perform detailed library characterization across multiple PVT conditions and technology nodes.
• Develop and analyse timing models including LVF, AOCV, POCV, and SOCV.
• Correlate timing signoff results across different EDA tools and against transistor-level SPICE simulations.
• Analyse correlation across timing, noise, Monte Carlo, variation, and other key silicon metrics.
• Evaluate timing accuracy and identify discrepancies between library models, signoff tools, and circuit-level simulations.
• Support timing signoff activities across advanced physical design flows.
• Work closely with Place & Route (P&R) and Static Timing Analysis (STA) teams to resolve timing and modelling issues.

Skills

ASIC timing analysis

Timing signoff

Library characterization

SPICE simulations

LVF timing models

AOCV/POCV/SOCV

EDA tools

Timing analysis

Education

Master's degree in Electrical/Electronic Engineering, Computer Engineering, Computer Science, or a related technical discipline

Tools

EDA tools

Job description

European Tech Recruit is seeking a Senior Timing Engineer for ASIC timing analysis, library characterization, and timing signoff across STA, LVF, AOCV/POCV/SOCV. You will work across library models, signoff tools, and SPICE simulations, coordinating with P&R and STA teams.

The role requires a Master’s degree and 3+ years of ASIC experience, with hands-on flows for library characterization and timing modelling.