Senior Timing Engineer — Sign-off & Variability Expert

European Tech Recruit; Munster; On-site; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Relocation package

Job summary

European Tech Recruit is seeking a Senior Timing Engineer in Ireland with a relocation package. You will develop, optimise and validate timing methodologies focusing on standard-cell library characterisation, timing models and sign-off flows.

You will work with SPICE extraction, aging/reliability models and STA, collaborating with synthesis and place-and-route teams to improve timing closure. The role requires hands-on experience with LVF and variation-aware timing, plus scripting in Python,

Qualifications

• Master's degree required in Electrical/ Electronic Engineering or related field.
• 3+ years of ASIC/semiconductor timing experience.
• Experience with standard-cell libraries and timing sign-off.
• Familiarity with LVF, POCV, SOCV and variation-aware timing.
• Proficient in Python, Perl, TCL or Bash scripting for automation.
• Experience with SPICE-based sign-off and aging/reliability modelling.

Responsibilities

• Develop and optimise timing methodologies for standard-cell libraries and models.
• Perform library characterisation and timing model development.
• Correlate timing sign-off results with SPICE simulations.
• Evaluate timing, noise, Monte Carlo and process variation.
• Automate engineering flows using Python, Perl, TCL and Bash.
• Collaborate with physical design teams across synthesis, place and route, and timing closure.

Skills

Timing methodologies

Sign-off

Standard-cell library characterisation

Variation-aware timing

SPICE simulations

STA

Python scripting

Perl scripting

TCL scripting

Bash scripting

Education

Master's degree in Electrical Engineering

Tools

EDA/CAD tools

Job description

European Tech Recruit is seeking a Senior Timing Engineer in Ireland with a relocation package. You will develop, optimise and validate timing methodologies focusing on standard-cell library characterisation, timing models and sign-off flows.

You will work with SPICE extraction, aging/reliability models and STA, collaborating with synthesis and place-and-route teams to improve timing closure. The role requires hands-on experience with LVF and variation-aware timing, plus scripting in Python,