Senior Timing Engineer - CAD tools / Physical Design

European Tech Recruit; Cork; On-site; EUR 90,000 - 130,000; Full time

Job summary

European Tech Recruit is seeking a Senior Timing Engineer to define, model, and implement IP for high performance, low power products. You will collaborate with software and hardware teams to ensure designs meet system requirements and customer needs.

The role requires deep timing knowledge, library characterisation experience, and strong scripting skills, with exposure to P&R/STA sign-off and modern CAD tools. Hybrid/onsite collaboration in Ireland is expected.

Qualifications

• Extensive experience in timing related activities, including library work, LVF, and AOCV/POCV/SOCV.
• Experience with CAD tools, including correlation between timing sign off tools and Spice simulation across metrics such as timing, noise, and Monte Carlo.
• Deep understanding of the library characterisation process and flow, with hands on experience characterising standard cell libraries.
• Strong scripting and automation skills (Python, Perl, TCL, Bash) to improve team productivity.
• Working knowledge of Spice extraction, modelling, and aging reliability models for the latest technology nodes.
• Proven knowledge of the latest technology nodes and practices in physical design, including Place and Route (P&R) and Static Timing Analysis (STA) sign off.
• Willingness to learn and contribute to developing and validating new methodologies.

Responsibilities

• Applying ASIC knowledge to define, model, design, optimise, verify, validate, implement, and document IP (block/SoC) for high performance, low power products
• Creating architectures, circuit specifications, logic designs, and system simulations based on system level requirements
• Collaborating across software and hardware architecture teams to develop and execute implementation strategies that meet system requirements and customer needs
• Evaluating all aspects of the process flow, from high level design through synthesis, place and route, timing, power use, and verification
• Using tools such as RTL to GDS flow and Virtuoso to execute architecture and design at block/SoC or IC package level
• Writing detailed technical documentation for EDA/IP/ASIC projects

Skills

Timing analysis

CAD tools

Scripting (Python)

Spice extraction/aging models

P&R/STA sign-off

Education

Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science

Tools

Virtuoso

Spice extraction tools

P&R tools

Job description

Senior Timing Engineer - CAD tools / Physical Design

Our client is a leading semiconductor technology innovator pushing the boundaries of what's possible to enable next generation experiences, driving transformation in communication and data processing to help build a smarter, connected future.

As a Senior Timing Engineer, you will define, model, design, optimise, verify, validate, implement, and document IP (block/SoC) for a range of high performance, high quality, low power products. You will collaborate closely with cross functional teams to help determine the product execution path.

What you will be doing

• Applying ASIC knowledge to define, model, design, optimise, verify, validate, implement, and document IP (block/SoC) for high performance, low power products
• Creating architectures, circuit specifications, logic designs, and system simulations based on system level requirements
• Collaborating across software and hardware architecture teams to develop and execute implementation strategies that meet system requirements and customer needs
• Evaluating all aspects of the process flow, from high level design through synthesis, place and route, timing, power use, and verification
• Using tools such as RTL to GDS flow and Virtuoso to execute architecture and design at block/SoC or IC package level
• Writing detailed technical documentation for EDA/IP/ASIC projects

What we are looking for

• Extensive experience in timing related activities, including library work, LVF, and AOCV/POCV/SOCV
• Experience with CAD tools, including correlation between timing sign off tools and Spice simulation across metrics such as timing, noise, and Monte Carlo
• Deep understanding of the library characterisation process and flow, with hands on experience characterising standard cell libraries
• Strong scripting and automation skills (Python, Perl, TCL, Bash) to improve team productivity
• Working knowledge of Spice extraction, modelling, and aging reliability models for the latest technology nodes
• Proven knowledge of the latest technology nodes and practices in physical design, including Place and Route (P&R) and Static Timing Analysis (STA) sign off
• Willingness to learn and contribute to developing and validating new methodologies

Preferred qualifications

• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science
• 3+ years of ASIC design, verification, validation, or integration experience
• 2+ years of experience with architecture and design tools
• 2+ years of experience with scripting tools and programming languages
• 2+ years of experience with design verification methods

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